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| * Augmented TimingAnalyser class with detection of clock to clock relationsMaciej Kurc2022-08-302-7/+225
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Fixed port timing classes of DCC ports in the Nexus architectureMaciej Kurc2022-08-301-4/+11
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | Merge pull request #1028 from YosysHQ/gatecat/router2-reserve-srcmyrtle2022-09-202-0/+17
|\ \ | | | | | | router2: Reserve source wire, too; ice40 fixes
| * | ice40: implement checkPipAvailForNetgatecat2022-09-201-0/+10
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | router2: Reserve source wire, toogatecat2022-09-201-0/+7
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | fabulous: fix, but disable, IO configurationgatecat2022-09-161-0/+3
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #1026 from YosysHQ/gatecat/ecp5-bitstream-refactormyrtle2022-09-161-1347/+1402
|\ \ | | | | | | ecp5: Split bitstream generation into more functions
| * | ecp5: Split bitstream generation into more functionsgatecat2022-09-151-1347/+1402
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #1023 from YosysHQ/gatecat/ice40up-bram-polmyrtle2022-09-161-3/+7
|\ \ \ | | | | | | | | ice40: Fix UltraPlus BRAM clock polarity
| * | | ice40: Fix UltraPlus BRAM clock polaritygatecat2022-09-141-3/+7
| | | | | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | | Merge pull request #1025 from YosysHQ/gatecat/nexus-dev-fixesmyrtle2022-09-153-1/+42
|\ \ \ \ | |_|/ / |/| | | nexus: Add ES2 device names and --list-devices
| * | | nexus: Add ES2 device names and --list-devicesgatecat2022-09-153-1/+42
|/ / / | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #1015 from YosysHQ/gatecat/fabulous-viaductmyrtle2022-09-1512-1/+1637
|\ \ \ | | | | | | | | fabulous: Add a viaduct uarch
| * | | fabulous: Add a viaduct uarchgatecat2022-09-0912-1/+1637
| | | | | | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | | Merge pull request #1024 from YosysHQ/gatecat/pybind11-bumpmyrtle2022-09-15214-10025/+21644
|\ \ \ \ | |_|/ / |/| | | 3rdparty: Bump vendored pybind11 version for py3.11 support
| * | | 3rdparty: Bump vendored pybind11 version for py3.11 supportgatecat2022-09-14214-10025/+21644
|/ / / | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #1018 from yrabbit/bf-0myrtle2022-08-251-0/+2
|\ \ \ | |_|/ |/| | gowin: BUGFIX. Really memorize the chip
| * | gowin: BUGFIX. Really memorize the chipYRabbit2022-08-251-0/+2
|/ / | | | | | | | | | | | | When it really needed to distinguish between the chips, this unforgivable error was discovered :) Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #1017 from YosysHQ/routerfixmyrtle2022-08-222-5/+4
|\ \ | | | | | | Router fix
| * | add missing overridesMiodrag Milanovic2022-08-221-3/+3
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| * | Fix parameter orderMiodrag Milanovic2022-08-221-2/+1
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* | Merge pull request #1016 from atsampson/python3myrtle2022-08-217-16/+16
|\ \ | | | | | | Use CMake's Python3 rather than PythonInterp in subdirs
| * | Use CMake's Python3 rather than PythonInterp in subdirsAdam Sampson2022-08-217-16/+16
|/ /
* | pybindings: Mark CellInfo::bel as readonlygatecat2022-08-181-2/+1
| | | | | | | | | | | | | | | | bel bindings should be updated with bindBel/unbindBel during placement, or setting the BEL attribute for constraints before placement. Fixes #522 Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #1014 from LAK132/mastermyrtle2022-08-181-4/+4
|\ \ | |/ |/| Replace deprecated method of finding Python 3
| * Replace deprecated method of finding Python 3LAK1322022-08-171-4/+4
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* Merge pull request #1013 from YosysHQ/gatecat/viaduct-argsmyrtle2022-08-151-0/+14
|\ | | | | viaduct: Allow passing command line options to uarch with -o
| * viaduct: Allow passing command line options to uarch with -ogatecat2022-08-151-0/+14
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1012 from YosysHQ/gatecat/refactor-id-inmyrtle2022-08-1124-203/+153
|\ | | | | refactor: Use IdString::in instead of || chains
| * refactor: Use IdString::in instead of || chainsgatecat2022-08-1024-203/+153
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1011 from YosysHQ/gatecat/nexus-lram-tmgmyrtle2022-08-103-0/+30
|\ | | | | nexus: Add timing data for LRAM
| * nexus: Add timing data for LRAMgatecat2022-08-103-0/+30
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1010 from YosysHQ/gatecat/idfmyrtle2022-08-1022-153/+152
|\ | | | | refactor: id(stringf(...)) to new idf(...) helper
| * refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-1022-153/+152
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1008 from YosysHQ/gatecat/generic-addbelpinmyrtle2022-08-043-25/+12
|\ | | | | generic: addBelPin with direction as an arg
| * generic: addBelPin with direction as an arggatecat2022-08-043-25/+12
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1004 from yrabbit/fix-muxesmyrtle2022-07-217-38/+26
|\ | | | | gowin: Remove incomprehensible names of the muxes
| * Merge branch 'master' into fix-muxesYRabbit2022-07-201-1/+1
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* | Merge pull request #1005 from YosysHQ/gatecat/nexus-ram-fixesmyrtle2022-07-191-1/+1
|\ \ | | | | | | nexus: Fix CSDECODE parsing
| * | nexus: Fix CSDECODE parsinggatecat2022-07-191-1/+1
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * gowin: fix compilationYRabbit2022-07-191-8/+0
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: Remove incomprehensible names of the muxesYRabbit2022-07-197-34/+30
|/ | | | | | | | | | | | There is no need to multiply item names, it is a rudiment of my very first addition to nextpnr. Fully compatible with older versions of Apicula. Note: the cosmetic changes in lines with RAM are not my initiative, but the result of applying clang-format. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #998 from yrabbit/clock-wipmyrtle2022-07-186-1/+479
|\ | | | | gowin: add a separate router for the clocks
| * Merge branch 'master' into clock-wipYRabbit2022-07-1016-49/+198
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* | Merge pull request #999 from YosysHQ/gatecat/pseudocell-apimyrtle2022-07-0816-49/+198
|\ \ | | | | | | netlist: Add PseudoCell API
| * | netlist: Add PseudoCell APIgatecat2022-07-0816-49/+198
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | When implementing concepts such as partition pins or deliberately split nets, there's a need for something that looks like a cell (starts/ends routing with pins on nets, has timing data) but isn't mapped to a fixed bel in the architecture, but instead can have pin mappings defined at runtime. The PseudoCell allows this by providing an alternate, virtual-function based API for such cells. When a cell has `pseudo_cell` used, instead of calling functions such as getBelPinWire, getBelLocation or getCellDelay in the Arch API; such data is provided by the cell itself, fully flexible at runtime regardless of arch, via methods on the PseudoCell implementation.
| * gowin: Remove unnecessary functionsYRabbit2022-07-052-33/+9
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * Merge branch 'master' into clock-wipYRabbit2022-07-059-106/+211
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* | Merge pull request #995 from pepijndevos/shadowrammyrtle2022-07-056-0/+187
|\ \ | | | | | | Gowin: WIP shadowram
| * | use DFF RAM modePepijn de Vos2022-07-021-1/+4
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