Merge pull request #1028 from YosysHQ/gatecat/router2-reserve-src

router2: Reserve source wire, too; ice40 fixes

2 files changed, 17 insertions, 0 deletions

diff --git a/common/route/router2.cc b/common/route/router2.cc
index d054c9ef..ed1a6fe0 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -453,6 +453,13 @@ struct Router2
     {
         bool did_something = false;
         WireId src = ctx->getNetinfoSourceWire(net);
+        {
+            auto &src_wd = wire_data(src);
+            if (src_wd.reserved_net != -1 && src_wd.reserved_net != net->udata)
+                log_error("attempting to reserve src wire '%s' for nets '%s' and '%s'\n", ctx->nameOfWire(src),
+                          ctx->nameOf(nets_by_udata.at(src_wd.reserved_net)), ctx->nameOf(net));
+            src_wd.reserved_net = net->udata;
+        }
         auto &usr = net->users.at(i);
         for (auto sink : ctx->getNetinfoSinkWires(net, usr)) {
             pool<WireId> rsv;
diff --git a/ice40/arch.h b/ice40/arch.h
index 3563baad..5ed2347d 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -680,6 +680,16 @@ struct Arch : BaseArch<ArchRanges>
         return switches_locked[pi.switch_index] == WireId();
     }
 
+    bool checkPipAvailForNet(PipId pip, NetInfo *net) const override
+    {
+        if (ice40_pip_hard_unavail(pip))
+            return false;
+
+        auto &pi = chip_info->pip_data[pip.index];
+        auto swl = switches_locked[pi.switch_index];
+        return swl == WireId() || (swl == getPipDstWire(pip) && wire_to_net[swl.index] == net);
+    }
+
     NetInfo *getBoundPipNet(PipId pip) const override
     {
         NPNR_ASSERT(pip != PipId());