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authormyrtle <gatecat@ds0.me>2022-08-22 13:31:11 +0200
committerGitHub <noreply@github.com>2022-08-22 13:31:11 +0200
commit0f4166fedbdba037256f25d0fa692f0487aa43f1 (patch)
treeee1ec8ae3823de798eab71f288e3262505b9740b
parentccf4367209986d7431217f8c3a3df1b71a601385 (diff)
parenta00b997cf19c0123f46f6509b2e42142e72f1d8c (diff)
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Merge pull request #1017 from YosysHQ/routerfix
Router fix
-rw-r--r--common/kernel/nextpnr_types.h6
-rw-r--r--common/route/router2.cc3
2 files changed, 4 insertions, 5 deletions
diff --git a/common/kernel/nextpnr_types.h b/common/kernel/nextpnr_types.h
index e4042aec..2a9062fd 100644
--- a/common/kernel/nextpnr_types.h
+++ b/common/kernel/nextpnr_types.h
@@ -205,9 +205,9 @@ struct RegionPlug : PseudoCell
WireId getPortWire(IdString port) const override { return port_wires.at(port); }
// TODO: partial reconfiguration region timing
- bool getDelay(IdString fromPort, IdString toPort, DelayQuad &delay) const { return false; }
- TimingPortClass getPortTimingClass(IdString port, int &clockInfoCount) const { return TMG_IGNORE; }
- virtual TimingClockingInfo getPortClockingInfo(IdString port, int index) const { return TimingClockingInfo{}; }
+ bool getDelay(IdString fromPort, IdString toPort, DelayQuad &delay) const override { return false; }
+ TimingPortClass getPortTimingClass(IdString port, int &clockInfoCount) const override { return TMG_IGNORE; }
+ TimingClockingInfo getPortClockingInfo(IdString port, int index) const override { return TimingClockingInfo{}; }
dict<IdString, WireId> port_wires;
Loc loc;
diff --git a/common/route/router2.cc b/common/route/router2.cc
index 1153f054..d054c9ef 100644
--- a/common/route/router2.cc
+++ b/common/route/router2.cc
@@ -373,8 +373,7 @@ struct Router2
return base_cost * hist_cost * present_cost / (1 + (source_uses * crit_weight)) + bias_cost;
}
- float get_togo_cost(NetInfo *net, store_index<PortRef> user, int wire, WireId src_sink, float crit_weight,
- bool bwd = false)
+ float get_togo_cost(NetInfo *net, store_index<PortRef> user, int wire, WireId src_sink, bool bwd, float crit_weight)
{
auto &nd = nets.at(net->udata);
auto &wd = flat_wires[wire];