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| author | myrtle <gatecat@ds0.me> | 2022-09-16 06:38:04 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-09-16 06:38:04 +0200 |
| commit | d58e85f29789cc7f5f93e1af6f8550b6f1ac83e7 (patch) | |
| tree | ce2bba7a5071a127981e0ef0a3eea6636deffc70 | |
| parent | e5da8be4f8feff179565b8784acc3b8d0a1ff3bb (diff) | |
| parent | 0a8c411692629b4748673b11f8dca8c3db7552fb (diff) | |
| download | nextpnr-d58e85f29789cc7f5f93e1af6f8550b6f1ac83e7.tar.gz nextpnr-d58e85f29789cc7f5f93e1af6f8550b6f1ac83e7.tar.bz2 nextpnr-d58e85f29789cc7f5f93e1af6f8550b6f1ac83e7.zip | |
Merge pull request #1023 from YosysHQ/gatecat/ice40up-bram-pol
ice40: Fix UltraPlus BRAM clock polarity
| -rw-r--r-- | ice40/bitstream.cc | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 3e50c065..2e1a6d4e 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -620,9 +620,13 @@ void write_asc(const Context *ctx, std::ostream &out) bool negclk_w = get_param_or_def(ctx, cell.second.get(), id_NEG_CLK_W); int write_mode = get_param_or_def(ctx, cell.second.get(), id_WRITE_MODE); int read_mode = get_param_or_def(ctx, cell.second.get(), id_READ_MODE); - set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w); - set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r); - + if (ctx->args.type == ArchArgs::UP5K || ctx->args.type == ArchArgs::UP3K) { + set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_r); + set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_w); + } else { + set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w); + set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r); + } set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_0", write_mode & 0x1); set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_1", write_mode & 0x2); set_config(ti_ramt, config.at(y + 1).at(x), "RamConfig.CBIT_2", read_mode & 0x1); |