| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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[FPGA interchange] Add support for global buffers from chipdb.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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[FPGA interchange] Convert some string constants to IdString.
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Also add some optional diagnostic prints for cell -> BEL pin mapping.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Initial inverter logic for FPGA interchange
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For now just implements some inspection capabilities, and the site
router (for now) avoids inverted paths.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Update parameter processing based on new DeviceResources metadata
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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interchange: Add nice error for missing cell pins
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Signed-off-by: gatecat <gatecat@ds0.me>
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Initial lookahead for FPGA interchange.
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Currently the lookahead is disabled by default because of the time to
compute and RAM usage. However it does appear to work reasonably well
in testing. Further effort is required to lower RAM usage after initial
computation, and explore trade-off for cheaper time to compute.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Correct some bugs in writing of physical netlist w.r.t. site sources.
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Local site sources should have their driving BEL pin included in the net
so that the site wire is driven by an output BEL pin.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Refine site router
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The new site router should be robust to most situations, and isn't
significantly slower with the use of caching.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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- Add additional targets useful for various situations.
- Have counter test use common remap.v file.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Add getBelPinType to Python interface.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Add "checkPipAvailForNet" to Arch API.
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This is important for distiguishing valid pseudo pips in the FPGA
interchange arch. This also avoids a double or triple lookup of
pip->net map.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Add pseudo pip data
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Refactor header structures in FPGA interchange Arch.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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cmake: Use IPO only if supported
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Signed-off-by: gatecat <gatecat@ds0.me>
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Update root CMake with some additional features
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Run "make clangformat" to fix up master.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Moving hash map/set type selection to header.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Add CMake infrastructure for fpga interchange
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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