iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	synth: handle verification units.	Tristan Gingold	2019-08-20	13	-246/+450
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*	synth: handle array attribute "length" (#895)	marph91	2019-08-19	1	-0/+10
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*	synth: fix tgingold/ghdlsynth#34 (association).	Tristan Gingold	2019-08-17	1	-2/+1
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*	vhdl: parse verification unit (WIP).	Tristan Gingold	2019-08-17	15	-363/+549
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*	synth: handle integer values in subtype conversion.	Tristan Gingold	2019-08-16	1	-0/+2
\| \| \| \|	For tgingold/ghdlsynth-beta#33
*	synth: handle integers for displaying vhdl ports.	Tristan Gingold	2019-08-16	1	-0/+10
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*	vhdl: declare verification units (WIP).	Tristan Gingold	2019-08-16	12	-280/+551
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*	vhdl: recognize PSL units reserved words.	Tristan Gingold	2019-08-16	6	-14/+29
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*	synth: handle array attributes; handle integer subtypes in generics.	Tristan Gingold	2019-08-16	2	-2/+91
\| \| \| \|	Fix tgingold/ghdlsynth-beta#32
*	add synthesis support for logic operators on numeric types (#893)	Pepijn de Vos	2019-08-15	4	-4/+149
\| \| \| \| \| \| \| \|	* add logic operators on unsigned * handle signed too * handle unary not
*	synth: fix handling of assume/assert.	Tristan Gingold	2019-08-14	1	-6/+65
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*	ghdlsynth: add command to get libghdl paths.	Tristan Gingold	2019-08-14	4	-22/+97
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*	ghdldrv: move command_str_disp from ghdlvpi to ghdlmain	Tristan Gingold	2019-08-14	3	-38/+38
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*	ghdlsynth: declare init_for_ghdl_synth.	Tristan Gingold	2019-08-14	1	-1/+4
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*	vhdl: handle PSL keywords as vhdl08 reserved words; switch to PSL scanner mode.	Tristan Gingold	2019-08-14	2	-0/+12
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*	vhdl: add PSL keywords to vhdl08 reserved words.	Tristan Gingold	2019-08-14	10	-242/+257
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*	synth: also extract edge in PSL expressions.	Tristan Gingold	2019-08-13	3	-18/+36
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*	synth: extract edge for PSL clocks.	Tristan Gingold	2019-08-13	1	-27/+34
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*	vhdl-nodes_walk: handle iir_kind_psl_default_clock.	Tristan Gingold	2019-08-13	1	-1/+2
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*	libghdlsynth: make it almost empty, as libghdl will be used instead.	Tristan Gingold	2019-08-13	1	-8/+0
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*	Support for PSL assert and assume in synthesis (#892)	Pepijn de Vos	2019-08-13	1	-4/+53
\| \| \| \| \| \| \| \|	* initial support for PSL assert and assume * add support for true, false, and, or in psl synth * update testsuite with new psl things
*	libghdl: also add synthesis part. For #884	Tristan Gingold	2019-08-13	6	-52/+56
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*	synth: build_header was replaced by a Makefile target.	Tristan Gingold	2019-08-13	1	-8/+0
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*	libghdl: preliminary work to also support synth.	Tristan Gingold	2019-08-13	2	-4/+9
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*	vhdl: improve reprint of inertial association.	Tristan Gingold	2019-08-11	6	-181/+206
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*	vhdl-sem: fix minor thinko for sem_insert_anonymous_signal.	Tristan Gingold	2019-08-11	1	-1/+24
\| \| \| \|	Fix #885
*	vhdl: avoid crash on incorrect unit name.	Tristan Gingold	2019-08-10	2	-6/+36
\| \| \| \|	Fix #886
*	vhdl: handle subtype indication (with range) in discrete_range.	Tristan Gingold	2019-08-10	7	-63/+105
\| \| \| \|	For #877
*	synth: add comments.	Tristan Gingold	2019-08-09	1	-1/+9
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*	vhdl: remove unused Get/Set_Choice_Order.	Tristan Gingold	2019-08-09	5	-304/+247
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*	synth: fix crash when assignment target is an aggregate.	Tristan Gingold	2019-08-08	1	-5/+7
\| \| \| \|	For tgingold/ghdlsynth-beta#26
*	vhdl: remove -Whides warnings for processes without a label.	Tristan Gingold	2019-08-08	1	-0/+9
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*	synth: handle 1 bit integer in disp_vhdl, fix range in synth-expr.	Tristan Gingold	2019-08-08	2	-4/+13
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*	vhdl: remove severity from cover, report and severity from assume.	Tristan Gingold	2019-08-08	11	-142/+160
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*	vhdl-nodes: gather PSL nodes, regenerate nodes_meta.	Tristan Gingold	2019-08-07	2	-125/+91
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*	Add support for PSL assumptions, used in formal verification (#880)	Pepijn de Vos	2019-08-07	30	-141/+334
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	* vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code
*	vhdl: allow discrete subtype indication for discrete_range.	Tristan Gingold	2019-08-06	5	-45/+53
\| \| \| \|	For #877
*	vhdl: for time resolution, do not consider unit name from textio body.	Tristan Gingold	2019-08-06	2	-10/+38
\| \| \| \|	For #881
*	synth: improve support of vhdl08. Fix #882	Tristan Gingold	2019-08-05	2	-5/+22
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*	synth: add asserts in synth-values	Tristan Gingold	2019-08-05	1	-0/+5
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*	synth: handle subtype conversions.	Tristan Gingold	2019-08-05	5	-73/+154
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*	synth: handle signed conversions in disp_vhdl.	Tristan Gingold	2019-08-05	1	-2/+6
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*	synth: preliminary support of integer literals.	Tristan Gingold	2019-08-02	2	-18/+67
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*	synth: add a debug procedure.	Tristan Gingold	2019-08-02	2	-0/+22
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*	synth: improve error message for multiple assignments.	Tristan Gingold	2019-08-02	1	-4/+20
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*	synth: handle signed integer comparisons (#878)	Pepijn de Vos	2019-08-01	3	-0/+43
\| \| \| \| \| \| \| \| \| \|	* comparisons with integer literals * display signed comparison nicely * revert literal size changes * properly display signed values
*	synth: handle partial assignments in a process (WIP).	Tristan Gingold	2019-08-01	1	-18/+75
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*	synth: refactoring in inference/environment.	Tristan Gingold	2019-08-01	3	-7/+13
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*	synth: refactor inference, add comment, strengthen check.	Tristan Gingold	2019-08-01	4	-31/+62
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*	synth: refactoring in synth-inference.	Tristan Gingold	2019-07-31	1	-129/+137
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