aboutsummaryrefslogtreecommitdiffstats
path: root/src
Commit message (Expand)AuthorAgeFilesLines
* simul: handle empty proceduresTristan Gingold2022-09-251-1/+9
* synth: rework association conversionsTristan Gingold2022-09-253-62/+75
* synth-vhdl_stmts: rework for subprogram associations (WIP)Tristan Gingold2022-09-251-57/+36
* synth-vhdl_stmts: support of individual paramater associations (WIP)Tristan Gingold2022-09-252-106/+238
* simul: reuse drivers extraction from elaborationTristan Gingold2022-09-252-74/+26
* synth-vhdl_stmts: refactore synth_subprogram_associationsTristan Gingold2022-09-251-49/+52
* synth-vhdl_stmts: refactoreTristan Gingold2022-09-251-23/+32
* synth-vhdl_stmts: refactoringTristan Gingold2022-09-251-189/+208
* synth-vhdl_stmts: rework in progress of subprogram associationsTristan Gingold2022-09-251-108/+115
* synth-vhdl_insts: move pragma unreferencedTristan Gingold2022-09-211-1/+2
* synth: simplify elab-vhdl_annotationsTristan Gingold2022-09-192-51/+3
* synth: simplify elab-vhdl_annotationsTristan Gingold2022-09-195-197/+31
* synth: rename vhdl.annotations to elab.vhdl_annotationsTristan Gingold2022-09-198-18/+20
* synth: rework subprogram associations (WIP)Tristan Gingold2022-09-193-42/+87
* synth-vhdl_stmts: minor renamingTristan Gingold2022-09-184-12/+12
* synth: fix assert failure on attribute specificationTristan Gingold2022-09-181-1/+5
* simul: handle individual port associations with expressionsTristan Gingold2022-09-181-1/+5
* simul: handle type conversions in port associationsTristan Gingold2022-09-183-49/+57
* synth: handle open variable associationTristan Gingold2022-09-171-22/+31
* simul: fix resolved associationTristan Gingold2022-09-172-2/+3
* simul: use synth_declarations for processes and proceduresTristan Gingold2022-09-174-18/+15
* synth: factorize code (reuse synth_constant_declaration)Tristan Gingold2022-09-178-71/+22
* synth: handle protected types in subprogramsTristan Gingold2022-09-173-38/+53
* synth: improve file handling (skip extra data, errors)Tristan Gingold2022-09-173-3/+53
* synth: finalize filesTristan Gingold2022-09-173-4/+30
* synth: handle read length on text filesTristan Gingold2022-09-171-16/+40
* synth: handle incomplete typesTristan Gingold2022-09-176-24/+87
* synth: handle individual generic associationsTristan Gingold2022-09-171-5/+35
* synth: factorize code with synth_assignment_prefixTristan Gingold2022-09-161-75/+15
* synth: preliminary work to factorize codeTristan Gingold2022-09-166-52/+69
* simul: handle active attributeTristan Gingold2022-09-164-11/+58
* synth: handle val attribute for static bit/logic valuesTristan Gingold2022-09-161-0/+3
* simul: improve support of concurrent procedure callTristan Gingold2022-09-161-1/+20
* simul: improve error handling during elaborationTristan Gingold2022-09-162-5/+6
* synth: improve handling of complex typesTristan Gingold2022-09-154-8/+30
* synth: handle vhdl-87 filesTristan Gingold2022-09-152-2/+14
* synth: handle access subtypesTristan Gingold2022-09-152-1/+9
* synth: handle read for files of unconstrained arraysTristan Gingold2022-09-153-1/+54
* simul: handle more signals typesTristan Gingold2022-09-152-23/+128
* trans-chap7: fix choice of exp. Fix #2189Tristan Gingold2022-09-151-3/+3
* ortho/mcode: add reg move for ret. Fix #2189Tristan Gingold2022-09-152-7/+17
* synth-vhdl_stmts: handle attribute names in expressionsTristan Gingold2022-09-141-1/+3
* simul: handle --expect-failure for elaborationTristan Gingold2022-09-143-11/+15
* synth: detect overflow in static exponentiationTristan Gingold2022-09-145-76/+265
* synth: add bounds check for float-integer type conversionTristan Gingold2022-09-121-2/+21
* simul: factorize code for conversion functionsTristan Gingold2022-09-121-19/+6
* simul: do not consider signal parameters as dynamic valuesTristan Gingold2022-09-123-1/+9
* synth: handle succ,pred,leftof,rightof attributesTristan Gingold2022-09-121-0/+95
* synth: improve handling of top-level interfaces subtypeTristan Gingold2022-09-117-20/+58
* synth: initialize out parameters of proceduresTristan Gingold2022-09-111-2/+9
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-13 10:31:32 +0000