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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-11 08:01:58 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-11 08:01:58 +0200 |
| commit | a67ead12564c47068e02fe702d07ad1ae2b832c9 (patch) | |
| tree | d74caabe80607780fd0ebb28fcc92fb011724c0b /src | |
| parent | be7f5722c79f15796326be6842339dca2d797539 (diff) | |
| download | ghdl-a67ead12564c47068e02fe702d07ad1ae2b832c9.tar.gz ghdl-a67ead12564c47068e02fe702d07ad1ae2b832c9.tar.bz2 ghdl-a67ead12564c47068e02fe702d07ad1ae2b832c9.zip | |
synth: initialize out parameters of procedures
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 6007fd975..d0234b814 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -2001,8 +2001,15 @@ package body Synth.Vhdl_Stmts is (Subprg_Inst, Val, Inter_Typ, True, Assoc); Val := Unshare (Val, Instance_Pool); else - -- Use default value ? - null; + -- Use default value + -- FIXME: also for wires ? + if Val.Val.Kind = Value_Memory then + if Is_Bounded_Type (Inter_Typ) then + Write_Value_Default (Val.Val.Mem, Inter_Typ); + else + Write_Value_Default (Val.Val.Mem, Val.Typ); + end if; + end if; end if; Val.Typ := Unshare (Val.Typ, Instance_Pool); when Iir_Kind_Interface_Signal_Declaration => |