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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-17 21:45:47 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-17 21:45:47 +0200 |
| commit | 6f258316773f74846c735daedc61817064737caf (patch) | |
| tree | 3380a8a8f5d086f343f9290aba97169b56263cda /src | |
| parent | 9756cfb38ea8ed8e9d1e92354ec8849b16bb00f1 (diff) | |
| download | ghdl-6f258316773f74846c735daedc61817064737caf.tar.gz ghdl-6f258316773f74846c735daedc61817064737caf.tar.bz2 ghdl-6f258316773f74846c735daedc61817064737caf.zip | |
simul: fix resolved association
Diffstat (limited to 'src')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 3 | ||||
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 2 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index b131d5462..b400a8106 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -614,7 +614,8 @@ package body Simul.Vhdl_Elab is if Get_Collapse_Signal_Flag (Assoc) and then Formal_Ep.Offs.Mem_Off = 0 and then Actual_Ep.Offs.Mem_Off = 0 - and then Actual_Base.Typ.W = Formal_Base.Typ.W + and then Actual_Base.Typ.W = Actual_Ep.Typ.W + and then Formal_Base.Typ.W = Formal_Ep.Typ.W then -- Full collapse. pragma Assert (Signals_Table.Table (Formal_Sig).Collapsed_By diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 2f3c2ef87..ebfdc17c8 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -2216,7 +2216,7 @@ package body Simul.Vhdl_Simul is Create_Signal (Val + Size_Type (I - 1) * Typ.Arr_El.Sz, Sig_Off + (Len - I) * Typ.Arr_El.W, El_Type, Typ.Arr_El, - Vec, Already_Resolved); + Vec, Sub_Resolved); end loop; end; when Type_Record => |