simul: do not consider signal parameters as dynamic values

3 files changed, 9 insertions, 1 deletions

diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index 344302aa3..646496a66 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -3043,6 +3043,7 @@ package body Simul.Vhdl_Simul is
       pragma Assert (Areapools.Is_Empty (Process_Pool));
 
       Synth.Flags.Severity_Level := Grt.Options.Severity_Level;
+      Synth.Flags.Flag_Simulation := True;
 
       if Flag_Interractive then
          Elab.Debugger.Debug_Elab (Vhdl_Elab.Top_Instance);
diff --git a/src/synth/synth-flags.ads b/src/synth/synth-flags.ads
index 211c01c1d..aa3a0b8aa 100644
--- a/src/synth/synth-flags.ads
+++ b/src/synth/synth-flags.ads
@@ -84,5 +84,10 @@ package Synth.Flags is
    --  If true, treat all PSL assume directives like assert directives
    Flag_Assume_As_Assert : Boolean := False;
 
+   --  If true, simulation is run instead of synthesis.  Consequences:
+   --  * signals value are known and can be read (through hooks).
+   --  * signals attributes are supported.
+   Flag_Simulation : Boolean := False;
+
    Flag_Verbose : Boolean := False;
 end Synth.Flags;
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb
index 04555a776..f2abd6df7 100644
--- a/src/synth/synth-vhdl_stmts.adb
+++ b/src/synth/synth-vhdl_stmts.adb
@@ -2067,7 +2067,9 @@ package body Synth.Vhdl_Stmts is
             return;
          end if;
 
-         if Get_Instance_Const (Subprg_Inst) and then not Is_Static (Val.Val)
+         if Get_Instance_Const (Subprg_Inst)
+           and then not Flags.Flag_Simulation
+           and then not Is_Static (Val.Val)
          then
             Set_Instance_Const (Subprg_Inst, False);
          end if;