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* synth-vhdl_insts: move pragma unreferencedTristan Gingold2022-09-211-1/+2
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* synth: simplify elab-vhdl_annotationsTristan Gingold2022-09-192-51/+3
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* synth: simplify elab-vhdl_annotationsTristan Gingold2022-09-195-197/+31
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* synth: rename vhdl.annotations to elab.vhdl_annotationsTristan Gingold2022-09-198-18/+20
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* synth: rework subprogram associations (WIP)Tristan Gingold2022-09-193-42/+87
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* synth-vhdl_stmts: minor renamingTristan Gingold2022-09-184-12/+12
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* synth: fix assert failure on attribute specificationTristan Gingold2022-09-181-1/+5
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* simul: handle individual port associations with expressionsTristan Gingold2022-09-181-1/+5
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* simul: handle type conversions in port associationsTristan Gingold2022-09-183-49/+57
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* synth: handle open variable associationTristan Gingold2022-09-171-22/+31
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* simul: fix resolved associationTristan Gingold2022-09-172-2/+3
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* simul: use synth_declarations for processes and proceduresTristan Gingold2022-09-174-18/+15
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* synth: factorize code (reuse synth_constant_declaration)Tristan Gingold2022-09-178-71/+22
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* synth: handle protected types in subprogramsTristan Gingold2022-09-173-38/+53
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* synth: improve file handling (skip extra data, errors)Tristan Gingold2022-09-173-3/+53
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* synth: finalize filesTristan Gingold2022-09-173-4/+30
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* synth: handle read length on text filesTristan Gingold2022-09-171-16/+40
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* synth: handle incomplete typesTristan Gingold2022-09-176-24/+87
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* synth: handle individual generic associationsTristan Gingold2022-09-171-5/+35
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* synth: factorize code with synth_assignment_prefixTristan Gingold2022-09-161-75/+15
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* synth: preliminary work to factorize codeTristan Gingold2022-09-166-52/+69
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* simul: handle active attributeTristan Gingold2022-09-164-11/+58
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* synth: handle val attribute for static bit/logic valuesTristan Gingold2022-09-161-0/+3
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* simul: improve support of concurrent procedure callTristan Gingold2022-09-161-1/+20
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* simul: improve error handling during elaborationTristan Gingold2022-09-162-5/+6
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* synth: improve handling of complex typesTristan Gingold2022-09-154-8/+30
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* synth: handle vhdl-87 filesTristan Gingold2022-09-152-2/+14
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* synth: handle access subtypesTristan Gingold2022-09-152-1/+9
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* synth: handle read for files of unconstrained arraysTristan Gingold2022-09-153-1/+54
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* simul: handle more signals typesTristan Gingold2022-09-152-23/+128
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* trans-chap7: fix choice of exp. Fix #2189Tristan Gingold2022-09-151-3/+3
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* ortho/mcode: add reg move for ret. Fix #2189Tristan Gingold2022-09-152-7/+17
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* synth-vhdl_stmts: handle attribute names in expressionsTristan Gingold2022-09-141-1/+3
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* simul: handle --expect-failure for elaborationTristan Gingold2022-09-143-11/+15
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* synth: detect overflow in static exponentiationTristan Gingold2022-09-145-76/+265
| | | | src/grt: extract grt.arith from grt.lib
* synth: add bounds check for float-integer type conversionTristan Gingold2022-09-121-2/+21
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* simul: factorize code for conversion functionsTristan Gingold2022-09-121-19/+6
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* simul: do not consider signal parameters as dynamic valuesTristan Gingold2022-09-123-1/+9
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* synth: handle succ,pred,leftof,rightof attributesTristan Gingold2022-09-121-0/+95
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* synth: improve handling of top-level interfaces subtypeTristan Gingold2022-09-117-20/+58
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* synth: initialize out parameters of proceduresTristan Gingold2022-09-111-2/+9
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* simul: move assertions (not to trigger in case of errors)Tristan Gingold2022-09-111-3/+3
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* simul: optimize resolution call only for std_logicTristan Gingold2022-09-111-5/+11
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* synth: fix and add checks for memory management.Tristan Gingold2022-09-1016-116/+362
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* simul: add support for protected objectsTristan Gingold2022-09-0812-23/+267
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* elab-vhdl_objtypes: handle bounded array base type. Fix #2187Tristan Gingold2022-09-081-1/+2
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* elab-vhdl_values: factorize codeTristan Gingold2022-09-076-29/+16
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* simul: do not propagate errors from resolution functionTristan Gingold2022-09-071-0/+3
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* synth-vhdl_stmts: fix handling of copyback parametersTristan Gingold2022-09-073-26/+38
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* elab-vhdl_stmts: fix a TODOTristan Gingold2022-09-071-1/+3
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