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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-11 08:00:53 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-11 08:00:53 +0200 |
| commit | c9eff2be46ac18d13ad003fd6724937b5691cff3 (patch) | |
| tree | 263a4236745915acca1f1c72d28237086d4052e0 /src | |
| parent | ff1ef30e8d370f89294e2d6e82fb1a15cdcd519c (diff) | |
| download | ghdl-c9eff2be46ac18d13ad003fd6724937b5691cff3.tar.gz ghdl-c9eff2be46ac18d13ad003fd6724937b5691cff3.tar.bz2 ghdl-c9eff2be46ac18d13ad003fd6724937b5691cff3.zip | |
simul: optimize resolution call only for std_logic
Diffstat (limited to 'src')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 5d86ee4a2..ed029cdf5 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -2056,19 +2056,25 @@ package body Simul.Vhdl_Simul is Already_Resolved : Boolean) is Sub_Resolved : Boolean := Already_Resolved; - Resolv_Func : Iir; + Resolv_Func : Node; Resolv_Instance : Resolv_Instance_Acc; S : Ghdl_Signal_Ptr; - Arr_Type : Iir; - Idx_Type : Iir; + Arr_Type : Node; + Idx_Type : Node; begin if not Already_Resolved and then Get_Kind (Sig_Type) in Iir_Kinds_Subtype_Definition then Resolv_Func := Get_Resolution_Indication (Sig_Type); - if Resolv_Func /= Null_Iir and then Vec (Sig_Off).Total > 1 then - Sub_Resolved := True; + if Resolv_Func /= Null_Node then Resolv_Func := Get_Named_Entity (Resolv_Func); + end if; + if Resolv_Func /= Null_Node + and then + (Vec (Sig_Off).Total > 1 + or else Resolv_Func /= Vhdl.Ieee.Std_Logic_1164.Resolved) + then + Sub_Resolved := True; Arr_Type := Get_Type (Get_Interface_Declaration_Chain (Resolv_Func)); Idx_Type := Vhdl.Utils.Get_Index_Type (Arr_Type, 0); |