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* vhdl: add a warning to detect use before elaborationTristan Gingold2023-01-158-5/+99
* vhdl: add Get/Set_Elaboration_FlagTristan Gingold2023-01-144-265/+326
* synth: more refactoringTristan Gingold2023-01-145-40/+40
* synth: improve error propagation on slicesTristan Gingold2023-01-145-9/+31
* synth-vhdl_stmts: introduce synth_individual_formalTristan Gingold2023-01-141-18/+107
* synth-vhdl_stmts: refactoringTristan Gingold2023-01-141-103/+131
* elab-vhdl_types(synth_record_type_definition): create unbounded recordTristan Gingold2023-01-141-3/+8
* elab-vhdl_debug: add option /t to print result typeTristan Gingold2023-01-141-5/+6
* synth-vhdl_eval: remove useless type unsharing for concatTristan Gingold2023-01-141-12/+4
* synth: handle protected functions in conversion functionsTristan Gingold2023-01-123-8/+17
* simul: handle PSL abortsTristan Gingold2023-01-123-0/+71
* synth: improve handling of 2008 aggregatesTristan Gingold2023-01-121-27/+142
* elab-vhdl_values-debug: improve output for array unboundedTristan Gingold2023-01-121-14/+21
* ghdlsimul: handle automatic time resolutionTristan Gingold2023-01-121-12/+17
* synth: handle generic mapped interface packageTristan Gingold2023-01-121-5/+17
* vhdl-sem_assocs(rewrite_non_object_association): set flagTristan Gingold2023-01-121-0/+1
* vhdl: clear associated_type in Sem_Generic_Association_ChainTristan Gingold2023-01-125-9/+90
* elab-vhdl_annotations(annotate_interface_list_subtype): adjustTristan Gingold2023-01-121-3/+15
* simul: fix handling of drivers/sensitivity within processesTristan Gingold2023-01-123-21/+25
* synth: fix handle of protected type bodies within instantiated packages.Tristan Gingold2023-01-123-3/+30
* elab-vhdl_types: improve handling of record subtypesTristan Gingold2023-01-122-18/+27
* ghdl_simul: add commands to use libghdlTristan Gingold2023-01-121-0/+2
* synth: handle operator as conversion functionTristan Gingold2023-01-121-1/+13
* vhdl-sem_names: finish prefix of element attribute namesTristan Gingold2023-01-121-22/+32
* synth: report values in bound errorsTristan Gingold2023-01-122-9/+40
* synth: use same wording for direction mismatch as simulationTristan Gingold2023-01-121-1/+2
* synth-vhdl_eval: handle to_X01 for bit to std_ulogic.Tristan Gingold2023-01-113-0/+39
* synth: handle entity attributesTristan Gingold2023-01-111-2/+18
* synth: handle universal r*i and i*r mul, physical mod.Tristan Gingold2023-01-111-1/+9
* synth: handle element attributeTristan Gingold2023-01-114-9/+39
* synth: fix matching comparaison tablesTristan Gingold2023-01-111-27/+27
* synth: rework error handling in file operationsTristan Gingold2023-01-113-43/+63
* simul: avoid a crash after an error in a conditionTristan Gingold2023-01-111-1/+6
* synth: improve support of PSL endpointsTristan Gingold2023-01-114-4/+8
* synth: avoid a crash on very large object typesTristan Gingold2023-01-111-0/+3
* synth: check float ranges in subtype conversionTristan Gingold2023-01-113-2/+25
* simul: allow function calls in signal association by valueTristan Gingold2023-01-111-0/+2
* synth: add a check for v87 concatenationsTristan Gingold2023-01-111-1/+6
* synth: support constant declarations in protected typesTristan Gingold2023-01-111-0/+1
* vhdl-configuration: relax top-level unit restrictionsTristan Gingold2023-01-111-4/+5
* synth: handle file subtypeTristan Gingold2023-01-112-1/+9
* simul: improve support of psl in debuggerTristan Gingold2023-01-112-4/+13
* simul: handle psl assume directivesTristan Gingold2023-01-111-0/+2
* simul: add sensitivity for psl processesTristan Gingold2023-01-111-4/+7
* synth: allow file declaration in protected objectsTristan Gingold2023-01-111-1/+2
* elab-vhdl_files: remove incorrect assertionTristan Gingold2023-01-111-1/+0
* simul: improve assertion messages for pslTristan Gingold2023-01-112-28/+45
* synth: avoid a crash after error on signal associationTristan Gingold2023-01-111-2/+6
* simul: add debug command 'run -s'Tristan Gingold2023-01-113-8/+18
* simul: handle array element resolutionTristan Gingold2023-01-111-1/+6
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