synth: improve error propagation on slices

5 files changed, 31 insertions, 9 deletions

diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index 0ff4d2446..69c81be35 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -536,7 +536,10 @@ package body Simul.Vhdl_Elab is
          exit when El = Null_Node;
          Sig := Compute_Sub_Signal (Inst, El);
 
-         Add_Process_Driver (Proc_Idx, Sig, El);
+         if Sig.Base /= No_Signal_Index then
+            --  Only if no error.
+            Add_Process_Driver (Proc_Idx, Sig, El);
+         end if;
 
          Next (It);
       end loop;
diff --git a/src/synth/elab-vhdl_expr.adb b/src/synth/elab-vhdl_expr.adb
index bef85b306..c43e3808e 100644
--- a/src/synth/elab-vhdl_expr.adb
+++ b/src/synth/elab-vhdl_expr.adb
@@ -480,11 +480,15 @@ package body Elab.Vhdl_Expr is
                Res_Bnd : Bound_Type;
                Sl_Off : Value_Offsets;
                Inp : Net;
+               Err : Boolean;
             begin
                Pfx_Typ := Exec_Name_Subtype (Syn_Inst, Get_Prefix (Name));
                Get_Onedimensional_Array_Bounds (Pfx_Typ, Pfx_Bnd, El_Typ);
                Synth_Slice_Suffix (Syn_Inst, Name, Pfx_Bnd, El_Typ,
-                                   Res_Bnd, Inp, Sl_Off);
+                                   Res_Bnd, Inp, Sl_Off, Err);
+               if Err then
+                  return null;
+               end if;
                pragma Assert (Inp = No_Net);
                return Create_Onedimensional_Array_Subtype
                  (Pfx_Typ, Res_Bnd, El_Typ);
diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb
index c330065a2..23665e8c1 100644
--- a/src/synth/synth-vhdl_expr.adb
+++ b/src/synth/synth-vhdl_expr.adb
@@ -1229,7 +1229,8 @@ package body Synth.Vhdl_Expr is
                                        Dir : Direction_Type;
                                        El_Typ : Type_Acc;
                                        Res_Bnd : out Bound_Type;
-                                       Off : out Value_Offsets)
+                                       Off : out Value_Offsets;
+                                       Error : out Boolean)
    is
       Is_Null : Boolean;
       Len : Uns32;
@@ -1243,6 +1244,7 @@ package body Synth.Vhdl_Expr is
          else
             Res_Bnd := (Dir => Dir_Downto, Left => 0, Right => 1, Len => 0);
          end if;
+         Error := True;
          return;
       end if;
 
@@ -1260,11 +1262,13 @@ package body Synth.Vhdl_Expr is
          if not In_Bounds (Pfx_Bnd, Int32 (L)) then
             Bound_Error (Syn_Inst, Expr, Pfx_Bnd, Int32 (L));
             Off := (0, 0);
+            Error := True;
             return;
          end if;
          if not In_Bounds (Pfx_Bnd, Int32 (R)) then
             Bound_Error (Syn_Inst, Expr, Pfx_Bnd, Int32 (R));
             Off := (0, 0);
+            Error := True;
             return;
          end if;
 
@@ -1283,6 +1287,7 @@ package body Synth.Vhdl_Expr is
                   Len => Len,
                   Left => Int32 (L),
                   Right => Int32 (R));
+      Error := False;
    end Synth_Slice_Const_Suffix;
 
    procedure Synth_Slice_Suffix (Syn_Inst : Synth_Instance_Acc;
@@ -1291,7 +1296,8 @@ package body Synth.Vhdl_Expr is
                                  El_Typ : Type_Acc;
                                  Res_Bnd : out Bound_Type;
                                  Inp : out Net;
-                                 Off : out Value_Offsets)
+                                 Off : out Value_Offsets;
+                                 Error : out Boolean)
    is
       Ctxt : constant Context_Acc := Get_Build (Syn_Inst);
       Expr : constant Node := Get_Suffix (Name);
@@ -1319,7 +1325,7 @@ package body Synth.Vhdl_Expr is
             Synth_Slice_Const_Suffix (Syn_Inst, Expr,
                                       Name, Pfx_Bnd,
                                       Rng.Left, Rng.Right, Rng.Dir,
-                                      El_Typ, Res_Bnd, Off);
+                                      El_Typ, Res_Bnd, Off, Error);
             return;
          end;
       end if;
@@ -1330,7 +1336,7 @@ package body Synth.Vhdl_Expr is
                                    Get_Static_Discrete (Left),
                                    Get_Static_Discrete (Right),
                                    Dir,
-                                   El_Typ, Res_Bnd, Off);
+                                   El_Typ, Res_Bnd, Off, Error);
       else
          if Pfx_Bnd.Dir /= Dir then
             Error_Msg_Synth (Syn_Inst, Name, "direction mismatch in slice");
@@ -1339,6 +1345,7 @@ package body Synth.Vhdl_Expr is
             else
                Res_Bnd := (Dir => Dir_Downto, Left => 0, Right => 1, Len => 0);
             end if;
+            Error := True;
             return;
          end if;
 
@@ -1346,6 +1353,7 @@ package body Synth.Vhdl_Expr is
             Error_Msg_Synth
               (Syn_Inst, Name, "left and right bounds of a slice must be "
                  & "either constant or dynamic");
+            Error := True;
             return;
          end if;
 
@@ -1353,6 +1361,7 @@ package body Synth.Vhdl_Expr is
                                    Get_Net (Ctxt, Left), Get_Net (Ctxt, Right),
                                    Inp, Step, Off.Net_Off, Res_Bnd.Len);
          if Inp = No_Net then
+            Error := True;
             return;
          end if;
          Inp_W := Get_Width (Inp);
@@ -1371,6 +1380,7 @@ package body Synth.Vhdl_Expr is
            (Ctxt, Inp, Step * El_Typ.W, Max,
             Inp_W + Width (Clog2 (Uns64 (Step * El_Typ.W))));
          Set_Location (Inp, Name);
+         Error := False;
       end if;
    end Synth_Slice_Suffix;
 
diff --git a/src/synth/synth-vhdl_expr.ads b/src/synth/synth-vhdl_expr.ads
index c991f388a..964c237f5 100644
--- a/src/synth/synth-vhdl_expr.ads
+++ b/src/synth/synth-vhdl_expr.ads
@@ -121,7 +121,8 @@ package Synth.Vhdl_Expr is
                                  El_Typ : Type_Acc;
                                  Res_Bnd : out Bound_Type;
                                  Inp : out Net;
-                                 Off : out Value_Offsets);
+                                 Off : out Value_Offsets;
+                                 Error : out Boolean);
 
    --  If VOFF is No_Net then OFF is valid, if VOFF is not No_Net then
    --  OFF is 0.
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb
index 649bd99fa..977741469 100644
--- a/src/synth/synth-vhdl_stmts.adb
+++ b/src/synth/synth-vhdl_stmts.adb
@@ -180,6 +180,7 @@ package body Synth.Vhdl_Stmts is
       Res_Bnd : Bound_Type;
       Sl_Voff : Net;
       Sl_Off : Value_Offsets;
+      Err : Boolean;
    begin
       if Dest_Base.Val /= null then
          Strip_Const (Dest_Base);
@@ -187,9 +188,12 @@ package body Synth.Vhdl_Stmts is
 
       Get_Onedimensional_Array_Bounds (Dest_Typ, Pfx_Bnd, El_Typ);
       Synth_Slice_Suffix (Syn_Inst, Pfx, Pfx_Bnd, El_Typ,
-                          Res_Bnd, Sl_Voff, Sl_Off);
+                          Res_Bnd, Sl_Voff, Sl_Off, Err);
 
-      if Sl_Voff = No_Net then
+      if Err then
+         Dest_Base := No_Valtyp;
+         Dest_Typ := null;
+      elsif Sl_Voff = No_Net then
          --  Fixed slice.
          Dest_Typ := Create_Onedimensional_Array_Subtype
            (Dest_Typ, Res_Bnd, El_Typ);