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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-11 05:56:55 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-11 05:56:55 +0100 |
| commit | f06d64e57d040cd851e2172f63609f77a5423d4f (patch) | |
| tree | 1a39b90b5ff392dd3704a90ad7c0da3d8557769f /src | |
| parent | c0a985bb4a50e42a80d177de03f529a4ca792895 (diff) | |
| download | ghdl-f06d64e57d040cd851e2172f63609f77a5423d4f.tar.gz ghdl-f06d64e57d040cd851e2172f63609f77a5423d4f.tar.bz2 ghdl-f06d64e57d040cd851e2172f63609f77a5423d4f.zip | |
simul: allow function calls in signal association by value
Diffstat (limited to 'src')
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 38cd2d925..989ae0e30 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -3544,6 +3544,7 @@ package body Simul.Vhdl_Simul is elsif Get_Expr_Staticness (Get_Actual (C.Assoc)) >= Globally then Mark_Expr_Pool (Marker); + Instance_Pool := Process_Pool'Access; Val := Synth.Vhdl_Expr.Synth_Expression_With_Type (C.Assoc_Inst, Get_Actual (C.Assoc), C.Formal.Typ); Val := Strip_Alias_Const (Val); @@ -3552,6 +3553,7 @@ package body Simul.Vhdl_Simul is C.Formal.Offs.Net_Off), C.Formal.Typ, Val.Val.Mem); + Instance_Pool := null; Release_Expr_Pool (Marker); end if; end if; |