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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-11 05:14:03 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-11 05:14:03 +0100 |
| commit | d7ce45a42f681d063373b75dd4fb5118e13de1c0 (patch) | |
| tree | 18fe26d06b114e8ce371c2680bb5f7ddb636357b /src | |
| parent | 8b2a821eb457c200db22443ba0b562b94d0d90b5 (diff) | |
| download | ghdl-d7ce45a42f681d063373b75dd4fb5118e13de1c0.tar.gz ghdl-d7ce45a42f681d063373b75dd4fb5118e13de1c0.tar.bz2 ghdl-d7ce45a42f681d063373b75dd4fb5118e13de1c0.zip | |
synth: avoid a crash after error on signal association
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/elab-vhdl_insts.adb | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/synth/elab-vhdl_insts.adb b/src/synth/elab-vhdl_insts.adb index 8e93fed84..26763a5c6 100644 --- a/src/synth/elab-vhdl_insts.adb +++ b/src/synth/elab-vhdl_insts.adb @@ -429,7 +429,9 @@ package body Elab.Vhdl_Insts is end case; end if; - Res := Unshare (Res, Global_Pool'Access); + if Res /= null then + Res := Unshare (Res, Global_Pool'Access); + end if; Release_Expr_Pool (Marker); return Res; else @@ -454,7 +456,9 @@ package body Elab.Vhdl_Insts is if Get_Whole_Association_Flag (Assoc) then Inter_Typ := Elab_Port_Association_Type (Sub_Inst, Syn_Inst, Inter, Assoc); - Create_Signal (Sub_Inst, Inter, Inter_Typ); + if Inter_Typ /= null then + Create_Signal (Sub_Inst, Inter, Inter_Typ); + end if; end if; Next_Association_Interface (Assoc, Assoc_Inter); end loop; |