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* vhdl-ieee-numeric: recognize vector/scalar operationsTristan Gingold2022-06-052-3/+51
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* synth-vhdl_oper: handle more bit_vector operations. Fix #2074Tristan Gingold2022-06-051-8/+13
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* elab-debugger: add where commandTristan Gingold2022-06-051-28/+49
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* synth-vhdl_eval: handle rotations and shift for numeric_stdTristan Gingold2022-06-051-4/+40
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* synth-vhdl_eval: handle to_x01, to_ux01, to_x01z and is_xTristan Gingold2022-06-052-19/+56
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* vhdl-ieee-numeric: recognize is_x, to_x01, to_ux01 and to_x01zTristan Gingold2022-06-052-8/+50
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* synth-vhdl_eval: handle more operationsTristan Gingold2022-06-053-2/+41
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* synth-ieee-numeric_std: fix handling of X for negationTristan Gingold2022-06-051-18/+20
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* synth-vhdl_eval: handle find_leftmost and find_rightmostTristan Gingold2022-06-053-0/+55
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* synth-vhdl_expr: adjust max computation for memidx. Fix #2073Tristan Gingold2022-06-052-3/+3
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* synth-vhdl_decls: fix subtype conversion for variable default value.Tristan Gingold2022-06-041-1/+1
| | | | Fix #2072
* synth-vhdl_eval: handle minmaxTristan Gingold2022-06-043-178/+295
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* vhdl: add a warning for unassociated portsTristan Gingold2022-06-044-9/+26
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* vhdl-sem_types: avoid a crash on empty records if forced analysisTristan Gingold2022-06-041-1/+9
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* synth-vhdl_expr: do not abort on array subtype conversionTristan Gingold2022-06-042-1/+6
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* vhdl-sem_scopes: handle state_suspendTristan Gingold2022-06-041-1/+2
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* elab-vhdl_debug: add print commandTristan Gingold2022-06-044-2/+306
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* synth-vhdl_eval: handle more operators (nand, nor, xnor)Tristan Gingold2022-06-042-0/+54
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* synth-vhdl_eval: add support for more operators.Tristan Gingold2022-06-043-24/+121
| | | | Fix some corner cases
* synth-vhdl_eval: handle rotationsTristan Gingold2022-06-043-1/+55
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* elab-vhdl_types: handle array attributes on function callTristan Gingold2022-06-042-0/+9
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* synth-vhdl_eval: handle more operations, fix resize corner caseTristan Gingold2022-06-032-24/+74
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* synth-vhdl_eval: handle more operationsTristan Gingold2022-06-033-4/+384
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* elab-debugger: remove duplicate flagTristan Gingold2022-06-035-10/+11
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* areapools: avoid a crash on release with empty blockTristan Gingold2022-06-031-0/+1
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* synth: handle file flush procedureTristan Gingold2022-06-013-0/+18
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* vhdl-ieee-std_logic_1164: recognize to_hstring, to_ostringTristan Gingold2022-06-012-0/+7
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* vhdl-utils(is_copyback_parameter): avoid a crash on file parameterTristan Gingold2022-06-011-6/+2
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* vhdl: improve use of interface types. For #2070Tristan Gingold2022-06-012-0/+6
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* vhdl-scanner: adjust assertion. For #2070Tristan Gingold2022-06-011-1/+1
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* vhdl-parse: do not allow nested context declaration. For #2070Tristan Gingold2022-06-011-1/+5
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* vhdl-parse: avoid a crash on too large numbers. For #2070Tristan Gingold2022-06-012-2/+15
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* vhdl: avoid crash after an error. For #2070Tristan Gingold2022-06-013-3/+10
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* vhdl-evaluation.adb: avoid a crash on overflow. For #2070Tristan Gingold2022-06-011-11/+12
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* vhdl-errors.adb: use normal message subprogram. For #2070Tristan Gingold2022-06-011-9/+1
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* synth-vhdl_eval: complete vector reduce operationsTristan Gingold2022-05-311-7/+21
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* synth-vhdl_eval: handle shift and rotationsTristan Gingold2022-05-311-6/+29
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* synth-vhdl_eval: handle vector match, numeric_bit.to_unsignedTristan Gingold2022-05-312-7/+73
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* vhdl: recognize numeric_bit.to_unsignedTristan Gingold2022-05-314-5/+57
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* synth-vhdl_stmts: do not convert out variable on callTristan Gingold2022-05-311-3/+8
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* synth-vhdl_stmts: export Synth_Subprogram_Back_AssociationTristan Gingold2022-05-312-7/+15
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* synth-vhdl_static_proc: handle write_realTristan Gingold2022-05-311-0/+32
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* synth-vhdl_eval: handle more operations (to_string, match)Tristan Gingold2022-05-312-23/+229
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* synth-vhdl_eval: handle more operatorsTristan Gingold2022-05-303-26/+402
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* synth-vhdl_static_proc: add hook for std.env.finishTristan Gingold2022-05-302-0/+12
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* synth-vhdl_oper: add hooks for bit edgeTristan Gingold2022-05-302-0/+15
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* vhdl-nodes: move maximum/minimum out of predefined operator rangeTristan Gingold2022-05-303-64/+67
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* elab-vhdl_objtypes: bit and logic types also have a rangeTristan Gingold2022-05-302-6/+13
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* synth-vhdl_eval: handle more operationsTristan Gingold2022-05-295-23/+219
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* synth-vhdl_eval: handle resolution_limitTristan Gingold2022-05-291-0/+3
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