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| author | Tristan Gingold <tgingold@free.fr> | 2022-06-04 08:54:14 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-06-04 16:27:48 +0200 |
| commit | 067cbd4ad02a724bcbe5cec50a7229787c1ae74c (patch) | |
| tree | bc12acc3696afc64d616afec4fb16a24102013ad /src | |
| parent | b36bdd7e0dc9988cd930631419c4ea53898ed7fd (diff) | |
| download | ghdl-067cbd4ad02a724bcbe5cec50a7229787c1ae74c.tar.gz ghdl-067cbd4ad02a724bcbe5cec50a7229787c1ae74c.tar.bz2 ghdl-067cbd4ad02a724bcbe5cec50a7229787c1ae74c.zip | |
synth-vhdl_eval: handle more operators (nand, nor, xnor)
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-ieee-std_logic_1164.ads | 39 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_eval.adb | 15 |
2 files changed, 54 insertions, 0 deletions
diff --git a/src/synth/synth-ieee-std_logic_1164.ads b/src/synth/synth-ieee-std_logic_1164.ads index 907cafa35..9b9531d89 100644 --- a/src/synth/synth-ieee-std_logic_1164.ads +++ b/src/synth/synth-ieee-std_logic_1164.ads @@ -75,6 +75,19 @@ package Synth.Ieee.Std_Logic_1164 is "UX0XXX0XX" -- - ); + Nand_Table : constant Table_2d := + -- UX01ZWLH- + ("UU1UUU1UU", -- U + "UX1XXX1XX", -- X + "111111111", -- 0 + "UX10XX10X", -- 1 + "UX1XXX1XX", -- Z + "UX1XXX1XX", -- W + "111111111", -- L + "UX10XX10X", -- H + "UX1XXX1XX" -- - + ); + Or_Table : constant Table_2d := -- UX01ZWLH- ("UUU1UUU1U", -- U @@ -88,6 +101,19 @@ package Synth.Ieee.Std_Logic_1164 is "UXX1XXX1X" -- - ); + Nor_Table : constant Table_2d := + -- UX01ZWLH- + ("UUU0UUU0U", -- U + "UXX0XXX0X", -- X + "UX10XX10X", -- 0 + "000000000", -- 1 + "UXX0XXX0X", -- Z + "UXX0XXX0X", -- W + "UX10XX10X", -- L + "000000000", -- H + "UXX0XXX0X" -- - + ); + Xor_Table : constant Table_2d := -- UX01ZWLH- ("UUUUUUUUU", -- U @@ -101,6 +127,19 @@ package Synth.Ieee.Std_Logic_1164 is "UXXXXXXXX" -- - ); + Xnor_Table : constant Table_2d := + -- UX01ZWLH- + ("UUUUUUUUU", -- U + "UXXXXXXXX", -- X + "UX10XX10X", -- 0 + "UX01XX01X", -- 1 + "UXXXXXXXX", -- Z + "UXXXXXXXX", -- W + "UX10XX10X", -- L + "UX01XX01X", -- H + "UXXXXXXXX" -- - + ); + Not_Table : constant Table_1d := -- UX01ZWLH- "UX10XX10X"; diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb index b14656b9e..d7a0c5694 100644 --- a/src/synth/synth-vhdl_eval.adb +++ b/src/synth/synth-vhdl_eval.adb @@ -762,16 +762,31 @@ package body Synth.Vhdl_Eval is | Iir_Predefined_Ieee_Numeric_Std_And_Sgn_Sgn => return Eval_Vector_Dyadic (Left, Right, And_Table, Expr); + when Iir_Predefined_Ieee_1164_Vector_Nand + | Iir_Predefined_Ieee_Numeric_Std_Nand_Uns_Uns + | Iir_Predefined_Ieee_Numeric_Std_Nand_Sgn_Sgn => + return Eval_Vector_Dyadic (Left, Right, Nand_Table, Expr); + when Iir_Predefined_Ieee_1164_Vector_Or | Iir_Predefined_Ieee_Numeric_Std_Or_Uns_Uns | Iir_Predefined_Ieee_Numeric_Std_Or_Sgn_Sgn => return Eval_Vector_Dyadic (Left, Right, Or_Table, Expr); + when Iir_Predefined_Ieee_1164_Vector_Nor + | Iir_Predefined_Ieee_Numeric_Std_Nor_Uns_Uns + | Iir_Predefined_Ieee_Numeric_Std_Nor_Sgn_Sgn => + return Eval_Vector_Dyadic (Left, Right, Nor_Table, Expr); + when Iir_Predefined_Ieee_1164_Vector_Xor | Iir_Predefined_Ieee_Numeric_Std_Xor_Uns_Uns | Iir_Predefined_Ieee_Numeric_Std_Xor_Sgn_Sgn => return Eval_Vector_Dyadic (Left, Right, Xor_Table, Expr); + when Iir_Predefined_Ieee_1164_Vector_Xnor + | Iir_Predefined_Ieee_Numeric_Std_Xnor_Uns_Uns + | Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn_Sgn => + return Eval_Vector_Dyadic (Left, Right, Xnor_Table, Expr); + when Iir_Predefined_Ieee_1164_Scalar_And => return Eval_Logic_Scalar (Left, Right, And_Table); when Iir_Predefined_Ieee_1164_Scalar_Or => |