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| author | Tristan Gingold <tgingold@free.fr> | 2022-05-30 04:08:30 +0200 | 
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-05-30 04:08:58 +0200 | 
| commit | f17aa58396cfd5c1851d9ff6f2a16a3dd0e44cc9 (patch) | |
| tree | ac5bdc9fa20dd3601e2c6c92759bebab9bcc2bea /src | |
| parent | 6607215b4ba19e42c2599cfa5c0313768013b845 (diff) | |
| download | ghdl-f17aa58396cfd5c1851d9ff6f2a16a3dd0e44cc9.tar.gz ghdl-f17aa58396cfd5c1851d9ff6f2a16a3dd0e44cc9.tar.bz2 ghdl-f17aa58396cfd5c1851d9ff6f2a16a3dd0e44cc9.zip  | |
elab-vhdl_objtypes: bit and logic types also have a range
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/elab-vhdl_objtypes.adb | 8 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_objtypes.ads | 11 | 
2 files changed, 13 insertions, 6 deletions
diff --git a/src/synth/elab-vhdl_objtypes.adb b/src/synth/elab-vhdl_objtypes.adb index 0b876ffeb..4815a495a 100644 --- a/src/synth/elab-vhdl_objtypes.adb +++ b/src/synth/elab-vhdl_objtypes.adb @@ -230,6 +230,10 @@ package body Elab.Vhdl_Objtypes is     begin        return To_Type_Acc (Alloc (Current_Pool, (Kind => Type_Bit,                                                  Wkind => Wkind_Net, +                                                Drange => (Left => 0, +                                                           Right => 1, +                                                           Dir => Dir_To, +                                                           Is_Signed => False),                                                  Al => 0,                                                  Sz => 1,                                                  W => 1))); @@ -242,6 +246,10 @@ package body Elab.Vhdl_Objtypes is     begin        return To_Type_Acc (Alloc (Current_Pool, (Kind => Type_Logic,                                                  Wkind => Wkind_Net, +                                                Drange => (Left => 0, +                                                           Right => 8, +                                                           Dir => Dir_To, +                                                           Is_Signed => False),                                                  Al => 0,                                                  Sz => 1,                                                  W => 1))); diff --git a/src/synth/elab-vhdl_objtypes.ads b/src/synth/elab-vhdl_objtypes.ads index 257065e5c..6d8554994 100644 --- a/src/synth/elab-vhdl_objtypes.ads +++ b/src/synth/elab-vhdl_objtypes.ads @@ -148,26 +148,25 @@ package Elab.Vhdl_Objtypes is        case Kind is           when Type_Bit -           | Type_Logic => -            null; -         when Type_Discrete => +            | Type_Logic +            | Type_Discrete =>              Drange : Discrete_Range_Type;           when Type_Float =>              Frange : Float_Range_Type;           when Type_Slice =>              Slice_El : Type_Acc;           when Type_Array -           | Type_Vector => +            | Type_Vector =>              Abound : Bound_Type;              Alast : Boolean;  --  True for the last dimension              Arr_El : Type_Acc;           when Type_Unbounded_Array -           | Type_Unbounded_Vector => +            | Type_Unbounded_Vector =>              Uarr_El : Type_Acc;              Ulast : Boolean;              Uarr_Idx : Type_Acc;           when Type_Record -           | Type_Unbounded_Record => +            | Type_Unbounded_Record =>              Rec : Rec_El_Array_Acc;           when Type_Access =>              Acc_Acc : Type_Acc;  | 
