synth-vhdl_eval: handle more operations

3 files changed, 41 insertions, 2 deletions

diff --git a/src/synth/synth-ieee-numeric_std.adb b/src/synth/synth-ieee-numeric_std.adb
index 221c9da6f..f2a9ac634 100644
--- a/src/synth/synth-ieee-numeric_std.adb
+++ b/src/synth/synth-ieee-numeric_std.adb
@@ -404,6 +404,21 @@ package body Synth.Ieee.Numeric_Std is
       return Add_Vec_Vec (L, R, False, Loc);
    end Add_Uns_Uns;
 
+   function Log_To_Vec (Val : Memtyp; Vec : Memtyp) return Memtyp
+   is
+      Len : constant Uns32 := Vec.Typ.Abound.Len;
+      Res : Memtyp;
+   begin
+      if Len = 0 then
+         --  FIXME: is it an error ?
+         return Vec;
+      end if;
+      Res := Create_Memory (Vec.Typ);
+      Fill (Res, '0');
+      Write_U8 (Res.Mem + Size_Type (Len - 1), Read_U8 (Val.Mem));
+      return Res;
+   end Log_To_Vec;
+
    function Add_Sgn_Sgn (L, R : Memtyp; Loc : Location_Type) return Memtyp is
    begin
       return Add_Vec_Vec (L, R, True, Loc);
diff --git a/src/synth/synth-ieee-numeric_std.ads b/src/synth/synth-ieee-numeric_std.ads
index 4c5888463..3431117c5 100644
--- a/src/synth/synth-ieee-numeric_std.ads
+++ b/src/synth/synth-ieee-numeric_std.ads
@@ -45,6 +45,10 @@ package Synth.Ieee.Numeric_Std is
    --  "abs"
    function Abs_Vec (V : Memtyp; Loc : Location_Type) return Memtyp;
 
+   --  Create a vector whose length is VEC'length, set to logic value VAL
+   --  at the lsb and filled with 0.
+   function Log_To_Vec (Val : Memtyp; Vec : Memtyp) return Memtyp;
+
    --  "+"
    function Add_Uns_Uns (L, R : Memtyp; Loc : Location_Type) return Memtyp;
    function Add_Sgn_Sgn (L, R : Memtyp; Loc : Location_Type) return Memtyp;
diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb
index f69fe6192..36e0c6c03 100644
--- a/src/synth/synth-vhdl_eval.adb
+++ b/src/synth/synth-vhdl_eval.adb
@@ -1080,12 +1080,17 @@ package body Synth.Vhdl_Eval is
             end;
 
          when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns
-           | Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log
-           | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log
            | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv
            | Iir_Predefined_Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv =>
             return Add_Uns_Uns (Left, Right, +Expr);
 
+         when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log
+           | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log =>
+            return Add_Uns_Uns (Left, Log_To_Vec (Right, Left), +Expr);
+
+         when Iir_Predefined_Ieee_Numeric_Std_Add_Log_Uns =>
+            return Add_Uns_Uns (Log_To_Vec (Left, Right), Right, +Expr);
+
          when Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat
            | Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int =>
             return Add_Uns_Nat (Left, To_Uns64 (Read_Discrete (Right)), +Expr);
@@ -1099,6 +1104,11 @@ package body Synth.Vhdl_Eval is
          when Iir_Predefined_Ieee_Numeric_Std_Add_Int_Sgn =>
             return Add_Sgn_Int (Right, Read_Discrete (Left), +Expr);
 
+         when Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Log =>
+            return Add_Sgn_Sgn (Left, Log_To_Vec (Right, Left), +Expr);
+         when Iir_Predefined_Ieee_Numeric_Std_Add_Log_Sgn =>
+            return Add_Sgn_Sgn (Log_To_Vec (Left, Right), Right, +Expr);
+
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns =>
             return Sub_Uns_Uns (Left, Right, +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat =>
@@ -1106,6 +1116,11 @@ package body Synth.Vhdl_Eval is
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Nat_Uns =>
             return Sub_Nat_Uns (To_Uns64 (Read_Discrete (Left)), Right, +Expr);
 
+         when Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Log =>
+            return Sub_Uns_Uns (Left, Log_To_Vec (Right, Left), +Expr);
+         when Iir_Predefined_Ieee_Numeric_Std_Sub_Log_Uns =>
+            return Sub_Uns_Uns (Log_To_Vec (Left, Right), Right, +Expr);
+
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Sgn =>
             return Sub_Sgn_Sgn (Left, Right, +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Int =>
@@ -1113,6 +1128,11 @@ package body Synth.Vhdl_Eval is
          when Iir_Predefined_Ieee_Numeric_Std_Sub_Int_Sgn =>
             return Sub_Int_Sgn (Read_Discrete (Left), Right, +Expr);
 
+         when Iir_Predefined_Ieee_Numeric_Std_Sub_Sgn_Log =>
+            return Sub_Sgn_Sgn (Left, Log_To_Vec (Right, Left), +Expr);
+         when Iir_Predefined_Ieee_Numeric_Std_Sub_Log_Sgn =>
+            return Sub_Sgn_Sgn (Log_To_Vec (Left, Right), Right, +Expr);
+
          when Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Uns =>
             return Mul_Uns_Uns (Left, Right, +Expr);
          when Iir_Predefined_Ieee_Numeric_Std_Mul_Nat_Uns =>