| Commit message (Expand) | Author | Age | Files | Lines |
* | synth: create sub-instace for processes | Tristan Gingold | 2023-01-20 | 5 | -6/+18 |
* | elab: Rename Get/Set_Info to Get/Set_Ann | Tristan Gingold | 2023-01-20 | 4 | -58/+59 |
* | synth: add partial support of foreign subprograms | Tristan Gingold | 2023-01-20 | 6 | -2/+363 |
* | std_names: add more AMS names | Tristan Gingold | 2023-01-18 | 2 | -1/+40 |
* | simul: handle PSL endpoints | Tristan Gingold | 2023-01-18 | 4 | -10/+38 |
* | simul: fix last_value for post vhdl 87 | Tristan Gingold | 2023-01-18 | 2 | -103/+145 |
* | synth-vhdl_eval: add an overflow check | Tristan Gingold | 2023-01-16 | 1 | -2/+6 |
* | synth: emit an error message on foreign subprogram calls | Tristan Gingold | 2023-01-16 | 1 | -0/+11 |
* | ghdlsimul: check foreign subprograms | Tristan Gingold | 2023-01-16 | 1 | -3/+4 |
* | vhdl: refactoring - remove trans_be, mainly added to vhdl-back_end | Tristan Gingold | 2023-01-16 | 9 | -274/+266 |
* | synth: handle invididual assoc with unbounded formals | Tristan Gingold | 2023-01-16 | 1 | -6/+130 |
* | simul: disable --trace-signals | Tristan Gingold | 2023-01-15 | 1 | -0/+4 |
* | synth: avoid a crash on instantiation | Tristan Gingold | 2023-01-15 | 1 | -4/+19 |
* | vhdl-sem.adb: also check elaboration status within package bodies | Tristan Gingold | 2023-01-15 | 1 | -6/+19 |
* | synth: avoid a crash on use before elaboration | Tristan Gingold | 2023-01-15 | 1 | -8/+16 |
* | synth: add Debug_Backtrace debug procedure | Tristan Gingold | 2023-01-15 | 2 | -0/+19 |
* | vhdl: add a warning to detect use before elaboration | Tristan Gingold | 2023-01-15 | 8 | -5/+99 |
* | vhdl: add Get/Set_Elaboration_Flag | Tristan Gingold | 2023-01-14 | 4 | -265/+326 |
* | synth: more refactoring | Tristan Gingold | 2023-01-14 | 5 | -40/+40 |
* | synth: improve error propagation on slices | Tristan Gingold | 2023-01-14 | 5 | -9/+31 |
* | synth-vhdl_stmts: introduce synth_individual_formal | Tristan Gingold | 2023-01-14 | 1 | -18/+107 |
* | synth-vhdl_stmts: refactoring | Tristan Gingold | 2023-01-14 | 1 | -103/+131 |
* | elab-vhdl_types(synth_record_type_definition): create unbounded record | Tristan Gingold | 2023-01-14 | 1 | -3/+8 |
* | elab-vhdl_debug: add option /t to print result type | Tristan Gingold | 2023-01-14 | 1 | -5/+6 |
* | synth-vhdl_eval: remove useless type unsharing for concat | Tristan Gingold | 2023-01-14 | 1 | -12/+4 |
* | synth: handle protected functions in conversion functions | Tristan Gingold | 2023-01-12 | 3 | -8/+17 |
* | simul: handle PSL aborts | Tristan Gingold | 2023-01-12 | 3 | -0/+71 |
* | synth: improve handling of 2008 aggregates | Tristan Gingold | 2023-01-12 | 1 | -27/+142 |
* | elab-vhdl_values-debug: improve output for array unbounded | Tristan Gingold | 2023-01-12 | 1 | -14/+21 |
* | ghdlsimul: handle automatic time resolution | Tristan Gingold | 2023-01-12 | 1 | -12/+17 |
* | synth: handle generic mapped interface package | Tristan Gingold | 2023-01-12 | 1 | -5/+17 |
* | vhdl-sem_assocs(rewrite_non_object_association): set flag | Tristan Gingold | 2023-01-12 | 1 | -0/+1 |
* | vhdl: clear associated_type in Sem_Generic_Association_Chain | Tristan Gingold | 2023-01-12 | 5 | -9/+90 |
* | elab-vhdl_annotations(annotate_interface_list_subtype): adjust | Tristan Gingold | 2023-01-12 | 1 | -3/+15 |
* | simul: fix handling of drivers/sensitivity within processes | Tristan Gingold | 2023-01-12 | 3 | -21/+25 |
* | synth: fix handle of protected type bodies within instantiated packages. | Tristan Gingold | 2023-01-12 | 3 | -3/+30 |
* | elab-vhdl_types: improve handling of record subtypes | Tristan Gingold | 2023-01-12 | 2 | -18/+27 |
* | ghdl_simul: add commands to use libghdl | Tristan Gingold | 2023-01-12 | 1 | -0/+2 |
* | synth: handle operator as conversion function | Tristan Gingold | 2023-01-12 | 1 | -1/+13 |
* | vhdl-sem_names: finish prefix of element attribute names | Tristan Gingold | 2023-01-12 | 1 | -22/+32 |
* | synth: report values in bound errors | Tristan Gingold | 2023-01-12 | 2 | -9/+40 |
* | synth: use same wording for direction mismatch as simulation | Tristan Gingold | 2023-01-12 | 1 | -1/+2 |
* | synth-vhdl_eval: handle to_X01 for bit to std_ulogic. | Tristan Gingold | 2023-01-11 | 3 | -0/+39 |
* | synth: handle entity attributes | Tristan Gingold | 2023-01-11 | 1 | -2/+18 |
* | synth: handle universal r*i and i*r mul, physical mod. | Tristan Gingold | 2023-01-11 | 1 | -1/+9 |
* | synth: handle element attribute | Tristan Gingold | 2023-01-11 | 4 | -9/+39 |
* | synth: fix matching comparaison tables | Tristan Gingold | 2023-01-11 | 1 | -27/+27 |
* | synth: rework error handling in file operations | Tristan Gingold | 2023-01-11 | 3 | -43/+63 |
* | simul: avoid a crash after an error in a condition | Tristan Gingold | 2023-01-11 | 1 | -1/+6 |
* | synth: improve support of PSL endpoints | Tristan Gingold | 2023-01-11 | 4 | -4/+8 |