simul: handle PSL endpoints

4 files changed, 38 insertions, 10 deletions

diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index 69c81be35..eb481479b 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -626,7 +626,8 @@ package body Simul.Vhdl_Elab is
             end if;
          when Iir_Kind_Psl_Assert_Directive
             | Iir_Kind_Psl_Assume_Directive
-            | Iir_Kind_Psl_Cover_Directive =>
+            | Iir_Kind_Psl_Cover_Directive
+            | Iir_Kind_Psl_Endpoint_Declaration =>
             List := Get_PSL_Clock_Sensitivity (Proc);
             Gather_Sensitivity (Inst, Proc_Idx, List);
             if Get_Kind (Proc) in Iir_Kinds_Psl_Property_Directive
@@ -935,12 +936,12 @@ package body Simul.Vhdl_Elab is
             --  Do not yet compute drivers or sensitivity as it may depends
             --  on declarations within the process.
          when Iir_Kind_Psl_Default_Clock
-           | Iir_Kind_Psl_Declaration
-           | Iir_Kind_Psl_Endpoint_Declaration =>
+           | Iir_Kind_Psl_Declaration =>
             null;
          when Iir_Kind_Psl_Assert_Directive
            | Iir_Kind_Psl_Assume_Directive
            | Iir_Kind_Psl_Cover_Directive
+           | Iir_Kind_Psl_Endpoint_Declaration
            | Iir_Kind_Concurrent_Break_Statement =>
             Processes_Table.Append ((Proc => Stmt,
                                      Inst => Inst,
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index d17ca0534..4e4061fef 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -562,6 +562,12 @@ package body Simul.Vhdl_Simul is
       return Hook_Quantity_Expr (Pfx.Obj);
    end Exec_Dot_Attribute;
 
+   function Exec_Endpoint (Inst : Synth_Instance_Acc;
+                           Expr : Node) return Valtyp is
+   begin
+      return Get_Value (Inst, Expr);
+   end Exec_Endpoint;
+
    procedure Execute_Sequential_Statements (Process : Process_State_Acc);
 
    function Execute_Condition (Inst : Synth_Instance_Acc;
@@ -2160,12 +2166,13 @@ package body Simul.Vhdl_Simul is
                   end if;
                   E.Done := True;
                end if;
---            when Iir_Kind_Psl_Endpoint_Declaration =>
---               declare
---                  Info : constant Sim_Info_Acc := Get_Info (E.Stmt);
---               begin
---                E.Instance.Objects (Info.Slot).B1 := Ghdl_B1 (Nvec (S_Num));
---               end;
+            when Iir_Kind_Psl_Endpoint_Declaration =>
+               declare
+                  Var : Valtyp;
+               begin
+                  Var := Get_Value (E.Instance, E.Proc);
+                  Write_U8 (Var.Val.Mem, Boolean'Pos (Nvec (S_Num)));
+               end;
             when others =>
                Vhdl.Errors.Error_Kind ("PSL_Process_Executer", E.Proc);
          end case;
@@ -2231,6 +2238,15 @@ package body Simul.Vhdl_Simul is
          when Iir_Kind_Psl_Cover_Directive =>
             --  TODO
             null;
+         when Iir_Kind_Psl_Endpoint_Declaration =>
+            declare
+               Val : Valtyp;
+            begin
+               Val := Create_Value_Memory (Bit_Type, Global_Pool'Access);
+               Write_Discrete (Val, 0);
+               --  TODO: create the object/signal during elaboration
+               Create_Object (Proc.Instance, Proc.Proc, Val);
+            end;
          when others =>
             null;
       end case;
@@ -2307,7 +2323,8 @@ package body Simul.Vhdl_Simul is
                Create_Process_Drivers (I);
 
             when Iir_Kind_Psl_Assert_Directive
-              | Iir_Kind_Psl_Cover_Directive =>
+               | Iir_Kind_Psl_Cover_Directive
+               | Iir_Kind_Psl_Endpoint_Declaration =>
                Processes_State (I) := (Kind => Kind_PSL,
                                        Has_State => False,
                                        Top_Instance => Instance,
@@ -4110,6 +4127,7 @@ package body Simul.Vhdl_Simul is
         Exec_Last_Event_Attribute'Access;
       Synth.Vhdl_Expr.Hook_Last_Active_Attribute :=
         Exec_Last_Active_Attribute'Access;
+      Synth.Vhdl_Expr.Hook_Endpoint := Exec_Endpoint'Access;
 
       Synth.Vhdl_Oper.Hook_Bit_Rising_Edge := Exec_Bit_Rising_Edge'Access;
       Synth.Vhdl_Oper.Hook_Bit_Falling_Edge := Exec_Bit_Falling_Edge'Access;
diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb
index d5a0e98fa..c4bd18868 100644
--- a/src/synth/synth-vhdl_expr.adb
+++ b/src/synth/synth-vhdl_expr.adb
@@ -812,6 +812,8 @@ package body Synth.Vhdl_Expr is
                Obj := Elab.Vhdl_Heap.Synth_Dereference (Acc);
                return Create_Value_Memtyp (Obj);
             end;
+         when Iir_Kind_Psl_Endpoint_Declaration =>
+            return Synth_Expression (Syn_Inst, Name);
          when others =>
             Error_Kind ("synth_name", Name);
       end case;
@@ -2621,6 +2623,12 @@ package body Synth.Vhdl_Expr is
             end if;
             Error_Msg_Synth (Syn_Inst, Expr, "dot attribute not allowed");
             return No_Valtyp;
+         when Iir_Kind_Psl_Endpoint_Declaration =>
+            if Hook_Endpoint /= null then
+               return Hook_Endpoint (Syn_Inst, Expr);
+            end if;
+            Error_Msg_Synth (Syn_Inst, Expr, "endpoint read not allowed");
+            return No_Valtyp;
          when others =>
             Error_Kind ("synth_expression_with_type", Expr);
       end case;
diff --git a/src/synth/synth-vhdl_expr.ads b/src/synth/synth-vhdl_expr.ads
index 964c237f5..cdffd0f68 100644
--- a/src/synth/synth-vhdl_expr.ads
+++ b/src/synth/synth-vhdl_expr.ads
@@ -95,6 +95,7 @@ package Synth.Vhdl_Expr is
    Hook_Last_Event_Attribute : Hook_Attribute_Acc;
    Hook_Last_Active_Attribute : Hook_Attribute_Acc;
    Hook_Dot_Attribute : Hook_Attribute_Acc;
+   Hook_Endpoint : Hook_Attribute_Acc;
 
    --  Use base type of EXPR to synthesize EXPR.  Useful when the type of
    --  EXPR is defined by itself or a range.