diff options
| author | Tristan Gingold <tgingold@free.fr> | 2023-01-18 19:33:06 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-18 19:33:06 +0100 |
| commit | 5bae163c99500d2395391a40b55d2c5618eaccd1 (patch) | |
| tree | 95bccde5f16e999df49a467e604c47ddc3493457 /src | |
| parent | d3e614c9ca81107ed059e5ed393a326265392f41 (diff) | |
| download | ghdl-5bae163c99500d2395391a40b55d2c5618eaccd1.tar.gz ghdl-5bae163c99500d2395391a40b55d2c5618eaccd1.tar.bz2 ghdl-5bae163c99500d2395391a40b55d2c5618eaccd1.zip | |
std_names: add more AMS names
Diffstat (limited to 'src')
| -rw-r--r-- | src/std_names.adb | 19 | ||||
| -rw-r--r-- | src/std_names.ads | 22 |
2 files changed, 40 insertions, 1 deletions
diff --git a/src/std_names.adb b/src/std_names.adb index 741a464d6..b82a7c549 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -366,6 +366,25 @@ package body Std_Names is Def ("s_until_with", Name_S_Until_With); Def ("until_with", Name_Until_With); + -- Verilog AMS + Def ("analog", Name_Analog); + Def ("discipline", Name_Discipline); + Def ("enddiscipline", Name_Enddiscipline); + Def ("endnature", Name_Endnature); + Def ("potential", Name_Potential); + Def ("flow", Name_Flow); + Def ("discrete", Name_Discrete); + Def ("continuous", Name_Continuous); + Def ("abstol", Name_Abstol); + Def ("ddt_nature", Name_Ddt_Nature); + Def ("idt_nature", Name_Idt_Nature); + Def ("branch", Name_Branch); + Def ("from", Name_From); + Def ("exclude", Name_Exclude); + Def ("ddt", Name_Ddt); + Def ("idt", Name_Idt); + Def ("white_noise", Name_White_Noise); + -- Create operators. Def ("=", Name_Op_Equality); Def ("/=", Name_Op_Inequality); diff --git a/src/std_names.ads b/src/std_names.ads index 97dff6d72..ccf073356 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -406,9 +406,29 @@ package Std_Names is Name_Until_With : constant Name_Id := Name_First_SV2009 + 3; Name_Last_SV2009 : constant Name_Id := Name_First_SV2009 + 3; + Name_First_Vams : constant Name_Id := Name_Last_SV2009 + 1; + Name_Analog : constant Name_Id := Name_First_Vams + 0; + Name_Discipline : constant Name_Id := Name_First_Vams + 1; + Name_Enddiscipline : constant Name_Id := Name_First_Vams + 2; + Name_Endnature : constant Name_Id := Name_First_Vams + 3; + Name_Potential : constant Name_Id := Name_First_Vams + 4; + Name_Flow : constant Name_Id := Name_First_Vams + 5; + Name_Discrete : constant Name_Id := Name_First_Vams + 6; + Name_Continuous : constant Name_Id := Name_First_Vams + 7; + Name_Abstol : constant Name_Id := Name_First_Vams + 8; + Name_Ddt_Nature : constant Name_Id := Name_First_Vams + 9; + Name_Idt_Nature : constant Name_Id := Name_First_Vams + 10; + Name_Branch : constant Name_Id := Name_First_Vams + 11; + Name_From : constant Name_Id := Name_First_Vams + 12; + Name_Exclude : constant Name_Id := Name_First_Vams + 13; + Name_Ddt : constant Name_Id := Name_First_Vams + 14; + Name_Idt : constant Name_Id := Name_First_Vams + 15; + Name_White_Noise : constant Name_Id := Name_First_Vams + 16; + Name_Last_Vams : constant Name_Id := Name_First_Vams + 16; + -- VHDL operators. Used as identifiers for declaration of overloaded -- operators. - Name_First_Operator : constant Name_Id := Name_Last_SV2009 + 1; + Name_First_Operator : constant Name_Id := Name_Last_Vams + 1; Name_Op_Equality : constant Name_Id := Name_First_Operator + 000; Name_Op_Inequality : constant Name_Id := Name_First_Operator + 001; Name_Op_Less : constant Name_Id := Name_First_Operator + 002; |