aboutsummaryrefslogtreecommitdiffstats
path: root/src/vhdl
Commit message (Collapse)AuthorAgeFilesLines
* vhdl-ams: fix overload for simple simultaneous statement.Tristan Gingold2019-12-293-4/+26
| | | | Fix tree consistency for branch quantity declarations.
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-2834-1058/+5972
|
* vhdl: add Has_Delay_Machanism for optional 'inertial' printing.Tristan Gingold2019-12-266-93/+165
|
* vhdl-prints: subtype indication is optional in object alias.Tristan Gingold2019-12-261-3/+2
|
* vhdl: handle non-object aliases in selected use clause. Fix #1057Tristan Gingold2019-12-241-5/+8
|
* vhdl: recognize ieee.std_logic_1164.is_x.Tristan Gingold2019-12-242-0/+9
|
* synth: support multiple synthesis.Tristan Gingold2019-12-022-0/+33
|
* vhdl: recognize sin and cos from math_real.Tristan Gingold2019-11-262-0/+6
|
* vhdl: recognize intrinsic procedures in vhdl-sem_specs.Tristan Gingold2019-11-232-25/+51
| | | | Fix synth failures for llvm and gcc backends.
* synth: preliminary work to support intrinsic procedures.Tristan Gingold2019-11-142-0/+26
|
* synth: file support (WIP).Tristan Gingold2019-11-121-1/+2
|
* synth: initial support for file types. For #1004Tristan Gingold2019-11-111-27/+33
|
* synth: initial support of access type. For #1004Tristan Gingold2019-11-111-0/+4
|
* vhdl-ieee-std_logic_1164: minor simplification.Tristan Gingold2019-11-061-21/+8
|
* synth: handle edge operators in synth_predefined_function_call.Tristan Gingold2019-11-062-5/+4
|
* vhdl: recognize rising_edge/falling_edge.Tristan Gingold2019-11-062-6/+15
|
* vhdl-scanner: handle 'synopsys' pragma.Tristan Gingold2019-11-041-1/+2
|
* vhdl-prints: handle more constructs in psl vunit.Tristan Gingold2019-10-311-0/+5
|
* vhdl: allow attributes in vunit declarations.Tristan Gingold2019-10-306-200/+216
|
* synth: handle concurrent signal assignment in vunits.Tristan Gingold2019-10-251-0/+2
|
* vhdl-canon: handle simple signal assignment in vunits.Tristan Gingold2019-10-251-273/+272
|
* vhdl-canon: extract canon_concurrent_label.Tristan Gingold2019-10-251-20/+25
|
* vhdl-annotations: extract annotate_concurrent_statement.Tristan Gingold2019-10-251-47/+53
|
* vhdl-annotations: minor renaming.Tristan Gingold2019-10-251-8/+8
|
* vhdl: extract sem_concurrent_statement, to handle hdl stmt in vunits.Tristan Gingold2019-10-254-119/+122
|
* vhdl-parse_psl: add comments.Tristan Gingold2019-10-251-8/+71
|
* vhdl-parse: do not scan PSL keywords in vunit declarations.Tristan Gingold2019-10-241-0/+4
|
* vhdl/translate: elaborate dependencies of configurations. Fix #984Tristan Gingold2019-10-241-0/+4
|
* vhdl-prints: do not crash on vunit declarations.Tristan Gingold2019-10-231-0/+4
|
* vhdl-annotations: handle some declarations in vunits.Tristan Gingold2019-10-231-0/+6
|
* vhdl-canon: handle some declarations in vunits.Tristan Gingold2019-10-231-2/+18
|
* vhdl-sem_psl: analyze some declarations.Tristan Gingold2019-10-231-0/+18
|
* vhdl-sem_decls: make sem_declaration public.Tristan Gingold2019-10-235-14/+31
|
* vhdl-sem_decls: extract sem_declaration.Tristan Gingold2019-10-231-121/+118
|
* vhdl-sem_decls: add comment.Tristan Gingold2019-10-211-0/+3
|
* vhdl-parse: parse declarations in vunit.Tristan Gingold2019-10-211-327/+352
|
* vhdl: handle labels in verification units.Tristan Gingold2019-10-211-8/+62
|
* psl: add active state.Tristan Gingold2019-10-211-0/+7
|
* vhdl-prints: handle restrict in vunit.Tristan Gingold2019-10-211-0/+2
|
* vhdl: try to convert identifier to token only for identifiersTristan Gingold2019-10-201-1/+3
| | | | | (and not for bit string literal). Fix #983
* vhdl-prints: add parenthesis around boolean and/or.Tristan Gingold2019-10-181-0/+4
|
* vhdl: check cover/restrict is followed by a sequence.Tristan Gingold2019-10-164-11/+65
|
* vhdl: Add the implicit [*] at start of PSL cover sequence.Tristan Gingold2019-10-151-0/+7
|
* vhdl: handle cover and restrict within vunit.Tristan Gingold2019-10-154-1/+15
|
* vhdl-evaluation: handle bit condition operator. Fix #977Tristan Gingold2019-10-131-0/+3
|
* vhdl-annotations: handle list of record elements declaration.Tristan Gingold2019-10-131-2/+4
|
* vhdl: recognize std_logic_unsigned.conv_integer.Tristan Gingold2019-10-132-0/+7
| | | | Handle more operators in synth.
* vhdl: recognize conv_integer functions from std_logic_arith.Tristan Gingold2019-10-112-18/+30
|
* vhdl: recognize std_logic_signed package (from synopsys).Tristan Gingold2019-10-114-14/+64
|
* vhdl: recognize minus from std_logic_unsignedTristan Gingold2019-10-112-0/+15
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 11:26:38 +0000