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| author | Tristan Gingold <tgingold@free.fr> | 2019-11-06 08:02:37 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-11-06 08:02:37 +0100 |
| commit | c6023180ffa061cf4394633642763b7d3546c737 (patch) | |
| tree | 6fdc9087b71fcaca2c57d38de83b83eafbf6b151 /src/vhdl | |
| parent | 3819515f724ed2ae81a1aa7b467359e26a3fb9e7 (diff) | |
| download | ghdl-c6023180ffa061cf4394633642763b7d3546c737.tar.gz ghdl-c6023180ffa061cf4394633642763b7d3546c737.tar.bz2 ghdl-c6023180ffa061cf4394633642763b7d3546c737.zip | |
vhdl: recognize rising_edge/falling_edge.
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_1164.adb | 18 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 3 |
2 files changed, 15 insertions, 6 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index 80c4c6ece..d88a45ccb 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -224,15 +224,22 @@ package body Vhdl.Ieee.Std_Logic_1164 is Decl := Get_Chain (Decl); exit when Decl = Null_Iir; - if Get_Kind (Decl) = Iir_Kind_Function_Declaration then + -- Recognize not-predefined functions. + if Get_Kind (Decl) = Iir_Kind_Function_Declaration + and then Get_Implicit_Definition (Decl) = Iir_Predefined_None + then + -- Useless assignment ? + Predefined := Iir_Predefined_None; + case Get_Identifier (Decl) is when Name_Rising_Edge => Rising_Edge := Decl; + Predefined := Iir_Predefined_Ieee_1164_Falling_Edge; when Name_Falling_Edge => Falling_Edge := Decl; + Predefined := Iir_Predefined_Ieee_1164_Falling_Edge; when Name_To_Bitvector => Predefined := Iir_Predefined_Ieee_1164_To_Bitvector; - Set_Implicit_Definition (Decl, Predefined); when others => if Is_Scalar_Scalar_Function (Decl) then case Get_Identifier (Decl) is @@ -251,7 +258,6 @@ package body Vhdl.Ieee.Std_Logic_1164 is when others => Predefined := Iir_Predefined_None; end case; - Set_Implicit_Definition (Decl, Predefined); elsif Is_Scalar_Function (Decl) then case Get_Identifier (Decl) is when Name_Not => @@ -262,7 +268,6 @@ package body Vhdl.Ieee.Std_Logic_1164 is when others => Predefined := Iir_Predefined_None; end case; - Set_Implicit_Definition (Decl, Predefined); elsif Is_Vector_Vector_Function (Decl) then case Get_Identifier (Decl) is when Name_And => @@ -280,7 +285,6 @@ package body Vhdl.Ieee.Std_Logic_1164 is when others => Predefined := Iir_Predefined_None; end case; - Set_Implicit_Definition (Decl, Predefined); elsif Is_Vector_Function (Decl) then case Get_Identifier (Decl) is when Name_Not => @@ -294,9 +298,11 @@ package body Vhdl.Ieee.Std_Logic_1164 is when others => Predefined := Iir_Predefined_None; end case; - Set_Implicit_Definition (Decl, Predefined); + else + Predefined := Iir_Predefined_None; end if; end case; + Set_Implicit_Definition (Decl, Predefined); end if; end loop; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index d02cddbc9..57b0675ff 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -4915,6 +4915,9 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_To_Bitvector, + Iir_Predefined_Ieee_1164_Rising_Edge, + Iir_Predefined_Ieee_1164_Falling_Edge, + -- VHDL-2008 unary logic operators Iir_Predefined_Ieee_1164_Vector_And_Reduce, Iir_Predefined_Ieee_1164_Vector_Or_Reduce, |