synth: support multiple synthesis.

2 files changed, 33 insertions, 0 deletions

diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb
index 9cf6d7931..6a4591430 100644
--- a/src/vhdl/vhdl-annotations.adb
+++ b/src/vhdl/vhdl-annotations.adb
@@ -16,6 +16,8 @@
 --  Software Foundation, 59 Temple Place - Suite 330, Boston, MA
 --  02111-1307, USA.
 
+with Ada.Unchecked_Deallocation;
+
 with Tables;
 with Simple_IO;
 with Vhdl.Std_Package;
@@ -1337,6 +1339,32 @@ package body Vhdl.Annotations is
       end case;
    end Annotate;
 
+   procedure Initialize_Annotate is
+   begin
+      Info_Node.Init;
+   end Initialize_Annotate;
+
+   procedure Finalize_Annotate
+   is
+      procedure Free is new Ada.Unchecked_Deallocation
+        (Sim_Info_Type, Sim_Info_Acc);
+   begin
+      Free (Global_Info);
+      for I in Info_Node.First .. Info_Node.Last loop
+         case Get_Kind (I) is
+            when Iir_Kind_Package_Body
+              | Iir_Kind_Function_Body
+              | Iir_Kind_Procedure_Body
+              | Iir_Kind_Protected_Type_Body =>
+               --  Info is shared with the spec.
+               null;
+            when others =>
+               Free (Info_Node.Table (I));
+         end case;
+      end loop;
+      Info_Node.Free;
+   end Finalize_Annotate;
+
    -- Disp annotations for an iir node.
    procedure Disp_Vhdl_Info (Node: Iir)
    is
diff --git a/src/vhdl/vhdl-annotations.ads b/src/vhdl/vhdl-annotations.ads
index be39173fe..3f0d42938 100644
--- a/src/vhdl/vhdl-annotations.ads
+++ b/src/vhdl/vhdl-annotations.ads
@@ -136,6 +136,11 @@ package Vhdl.Annotations is
       end case;
    end record;
 
+   --  The first initialization is done automatically, but must be done again
+   --  after finalization.
+   procedure Initialize_Annotate;
+   procedure Finalize_Annotate;
+
    --  Decorate the tree in order to be usable with the internal simulator.
    procedure Annotate (Unit : Iir_Design_Unit);