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author | Tristan Gingold <tgingold@free.fr> | 2019-10-11 06:57:27 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-11 06:57:27 +0200 |
commit | 966ffd5b0317e61f5b4e48c2e43889d055ddddcc (patch) | |
tree | 5f925a30e8193be7cf733c5dee1dbb66fe71a568 /src/vhdl | |
parent | bca8844670a1a13964f42dc4223f720c4f405939 (diff) | |
download | ghdl-966ffd5b0317e61f5b4e48c2e43889d055ddddcc.tar.gz ghdl-966ffd5b0317e61f5b4e48c2e43889d055ddddcc.tar.bz2 ghdl-966ffd5b0317e61f5b4e48c2e43889d055ddddcc.zip |
vhdl: recognize conv_integer functions from std_logic_arith.
Diffstat (limited to 'src/vhdl')
-rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_arith.adb | 41 | ||||
-rw-r--r-- | src/vhdl/vhdl-nodes.ads | 7 |
2 files changed, 30 insertions, 18 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_arith.adb b/src/vhdl/vhdl-ieee-std_logic_arith.adb index abb7218d2..28bf913a1 100644 --- a/src/vhdl/vhdl-ieee-std_logic_arith.adb +++ b/src/vhdl/vhdl-ieee-std_logic_arith.adb @@ -27,8 +27,23 @@ package body Vhdl.Ieee.Std_Logic_Arith is Unsigned_Type : Iir := Null_Iir; Signed_Type : Iir := Null_Iir; - type Arg_Kind is (Type_Signed, Type_Unsigned, Type_Int, - Type_Log, Type_Slv); + type Arg_Kind is (Type_Signed, Type_Unsigned, Type_Int, Type_Log, Type_Slv); + + subtype Conv_Arg_Kind is Arg_Kind range Type_Signed .. Type_Log; + type Conv_Pattern_Type is + array (Conv_Arg_Kind) of Iir_Predefined_Functions; + + Conv_Uns_Patterns : constant Conv_Pattern_Type := + (Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Log); + + Conv_Int_Patterns : constant Conv_Pattern_Type := + (Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Log); Error : exception; @@ -59,24 +74,14 @@ package body Vhdl.Ieee.Std_Logic_Arith is Arg1, Arg2 : Iir; Arg1_Kind, Arg2_Kind : Arg_Kind; - function Handle_Conv_Unsigned return Iir_Predefined_Functions is + function Handle_Conv (Pats : Conv_Pattern_Type) + return Iir_Predefined_Functions is begin if Arg2_Kind /= Type_Int then raise Error; end if; - case Arg1_Kind is - when Type_Int => - return Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int; - when Type_Unsigned => - return Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Uns; - when Type_Signed => - return Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn; - when Type_Log => - return Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Log; - when others => - raise Error; - end case; - end Handle_Conv_Unsigned; + return Pats (Arg1_Kind); + end Handle_Conv; Def : Iir_Predefined_Functions; begin @@ -146,13 +151,15 @@ package body Vhdl.Ieee.Std_Logic_Arith is case Get_Identifier (Decl) is when Name_Conv_Unsigned => - Def := Handle_Conv_Unsigned; + Def := Handle_Conv (Conv_Uns_Patterns); when others => null; end case; else -- Monadic function. case Get_Identifier (Decl) is + when Name_Conv_Integer => + Def := Conv_Int_Patterns (Arg1_Kind); when others => null; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 44d25880d..bd25fb805 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5110,7 +5110,12 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Uns, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn, - Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Log + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Log, + + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Int, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Sgn, + Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Log ); -- Return TRUE iff FUNC is a short-cut predefined function. |