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* vhdl-parse_psl: add comments.Tristan Gingold2019-10-251-8/+71
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* vhdl-parse: do not scan PSL keywords in vunit declarations.Tristan Gingold2019-10-241-0/+4
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* vhdl/translate: elaborate dependencies of configurations. Fix #984Tristan Gingold2019-10-241-0/+4
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* vhdl-prints: do not crash on vunit declarations.Tristan Gingold2019-10-231-0/+4
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* vhdl-annotations: handle some declarations in vunits.Tristan Gingold2019-10-231-0/+6
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* vhdl-canon: handle some declarations in vunits.Tristan Gingold2019-10-231-2/+18
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* vhdl-sem_psl: analyze some declarations.Tristan Gingold2019-10-231-0/+18
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* vhdl-sem_decls: make sem_declaration public.Tristan Gingold2019-10-235-14/+31
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* vhdl-sem_decls: extract sem_declaration.Tristan Gingold2019-10-231-121/+118
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* vhdl-sem_decls: add comment.Tristan Gingold2019-10-211-0/+3
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* vhdl-parse: parse declarations in vunit.Tristan Gingold2019-10-211-327/+352
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* vhdl: handle labels in verification units.Tristan Gingold2019-10-211-8/+62
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* psl: add active state.Tristan Gingold2019-10-211-0/+7
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* vhdl-prints: handle restrict in vunit.Tristan Gingold2019-10-211-0/+2
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* vhdl: try to convert identifier to token only for identifiersTristan Gingold2019-10-201-1/+3
| | | | | (and not for bit string literal). Fix #983
* vhdl-prints: add parenthesis around boolean and/or.Tristan Gingold2019-10-181-0/+4
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* vhdl: check cover/restrict is followed by a sequence.Tristan Gingold2019-10-164-11/+65
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* vhdl: Add the implicit [*] at start of PSL cover sequence.Tristan Gingold2019-10-151-0/+7
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* vhdl: handle cover and restrict within vunit.Tristan Gingold2019-10-154-1/+15
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* vhdl-evaluation: handle bit condition operator. Fix #977Tristan Gingold2019-10-131-0/+3
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* vhdl-annotations: handle list of record elements declaration.Tristan Gingold2019-10-131-2/+4
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* vhdl: recognize std_logic_unsigned.conv_integer.Tristan Gingold2019-10-132-0/+7
| | | | Handle more operators in synth.
* vhdl: recognize conv_integer functions from std_logic_arith.Tristan Gingold2019-10-112-18/+30
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* vhdl: recognize std_logic_signed package (from synopsys).Tristan Gingold2019-10-114-14/+64
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* vhdl: recognize minus from std_logic_unsignedTristan Gingold2019-10-112-0/+15
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* vhdl: do not try to recognize mentor version of std_logic_arith.Tristan Gingold2019-10-101-0/+7
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* vhdl: recognize conv_unsigned from ieee.std_logic_arith.Tristan Gingold2019-10-104-1/+201
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* synth: handle package bodies.Tristan Gingold2019-10-071-0/+1
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* vhdl: recognize to_bitvector.Tristan Gingold2019-10-072-81/+74
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* synth: add support for concurrent procedure calls. Fix #969Tristan Gingold2019-10-071-1/+2
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* Rework errors handling, to have a more generic framework.Tristan Gingold2019-10-062-4/+61
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* synth: improve support of arrays or arrays. Fix #955Tristan Gingold2019-10-011-13/+8
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* vhdl: recognize div operators.Tristan Gingold2019-09-302-0/+27
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* vhdl-std_package: reduce cascaded error messages.Tristan Gingold2019-09-301-0/+1
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* vhdl: recognize rotate functions.Tristan Gingold2019-09-222-0/+17
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* synth: handle record subtypes.Tristan Gingold2019-09-191-5/+8
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* vhdl: add exit/next flags.Tristan Gingold2019-09-185-63/+173
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* vhdl-nodes: add a comment.Tristan Gingold2019-09-121-1/+1
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* vhdl-ieee-numeric: recognize shift_right.Tristan Gingold2019-09-111-17/+31
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* vhdl: recognize numeric_std shift_left.Tristan Gingold2019-09-112-0/+24
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* vhdl: recognize numeric_std mul.Tristan Gingold2019-09-072-0/+27
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* vhdl: fix unused warning on protected variable.Tristan Gingold2019-09-061-0/+1
| | | | Fix ghdl/ghdl-language-server#27
* vhdl: handle P32 in connect_scalar. Fix #918Tristan Gingold2019-09-051-1/+2
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* vhdl: do not crash on attribute with a type conversion prefix.Tristan Gingold2019-09-041-2/+3
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* vhdl: renames Conditional_Expression to Conditional_Expression_Chain.Tristan Gingold2019-09-028-37/+40
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* vhdl synth: recognize more operators (add uns log).Tristan Gingold2019-09-022-2/+6
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* vhdl-annotations: ignore conditional variable assignment.Tristan Gingold2019-08-301-1/+2
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* vhdl-annotate: handle shared anonymous subtype in interfaces.Tristan Gingold2019-08-301-1/+4
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* vhdl: recognize ieee.numeric_std std_match.Tristan Gingold2019-08-302-0/+39
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* vhdl: recognize 1164 condition operator, handle in synth.Tristan Gingold2019-08-302-5/+17
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