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authorTristan Gingold <tgingold@free.fr>2019-09-01 10:48:43 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-02 20:40:55 +0200
commitc6ee7f41e2f86d8d46cd559f32cd290b99b46178 (patch)
tree77c8c1afcedc5bff142d44517d31184295ad2b63 /src/vhdl
parentfcdd43d1bc6834408b3f16a654bc0cddf4533c5e (diff)
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vhdl synth: recognize more operators (add uns log).
Diffstat (limited to 'src/vhdl')
-rw-r--r--src/vhdl/vhdl-ieee-numeric.adb4
-rw-r--r--src/vhdl/vhdl-nodes.ads4
2 files changed, 6 insertions, 2 deletions
diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb
index a1ac7927e..cf0f7db26 100644
--- a/src/vhdl/vhdl-ieee-numeric.adb
+++ b/src/vhdl/vhdl-ieee-numeric.adb
@@ -43,8 +43,8 @@ package body Vhdl.Ieee.Numeric is
(Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns,
Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat,
Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Add_Nat_Uns,
- Arg_Vect_Log => Iir_Predefined_None,
- Arg_Log_Vect => Iir_Predefined_None),
+ Arg_Vect_Log => Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log,
+ Arg_Log_Vect => Iir_Predefined_Ieee_Numeric_Std_Add_Log_Uns),
Type_Signed =>
(Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Sgn,
Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int,
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index 3a2bcb20b..fe7b89066 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -4927,9 +4927,13 @@ package Vhdl.Nodes is
Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns,
Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Nat,
Iir_Predefined_Ieee_Numeric_Std_Add_Nat_Uns,
+ Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Log,
+ Iir_Predefined_Ieee_Numeric_Std_Add_Log_Uns,
Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Sgn,
Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Int,
Iir_Predefined_Ieee_Numeric_Std_Add_Int_Sgn,
+ Iir_Predefined_Ieee_Numeric_Std_Add_Sgn_Log,
+ Iir_Predefined_Ieee_Numeric_Std_Add_Log_Sgn,
Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Uns,
Iir_Predefined_Ieee_Numeric_Std_Sub_Uns_Nat,