aboutsummaryrefslogtreecommitdiffstats
path: root/src/vhdl
diff options
context:
space:
mode:
authorTristan Gingold <tgingold@free.fr>2019-10-07 18:58:04 +0200
committerTristan Gingold <tgingold@free.fr>2019-10-07 18:58:04 +0200
commit167a6d0c0c9bdcc6381183e4913df7ccab03269e (patch)
tree0d8b29079de198685f9699bcac68f78b8a8457ff /src/vhdl
parentcdda9d783f71a13fa2c828f6b8677f64932f6a6e (diff)
downloadghdl-167a6d0c0c9bdcc6381183e4913df7ccab03269e.tar.gz
ghdl-167a6d0c0c9bdcc6381183e4913df7ccab03269e.tar.bz2
ghdl-167a6d0c0c9bdcc6381183e4913df7ccab03269e.zip
vhdl: recognize to_bitvector.
Diffstat (limited to 'src/vhdl')
-rw-r--r--src/vhdl/vhdl-ieee-std_logic_1164.adb153
-rw-r--r--src/vhdl/vhdl-nodes.ads2
2 files changed, 74 insertions, 81 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb
index 7ea7da787..80c4c6ece 100644
--- a/src/vhdl/vhdl-ieee-std_logic_1164.adb
+++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb
@@ -122,6 +122,7 @@ package body Vhdl.Ieee.Std_Logic_1164 is
Decl : Iir;
Def : Iir;
+ Predefined : Iir_Predefined_Functions;
begin
Std_Logic_1164_Pkg := Pkg;
@@ -224,88 +225,78 @@ package body Vhdl.Ieee.Std_Logic_1164 is
exit when Decl = Null_Iir;
if Get_Kind (Decl) = Iir_Kind_Function_Declaration then
- if Get_Identifier (Decl) = Name_Rising_Edge then
- Rising_Edge := Decl;
- elsif Get_Identifier (Decl) = Name_Falling_Edge then
- Falling_Edge := Decl;
- elsif Is_Scalar_Scalar_Function (Decl) then
- declare
- Predefined : Iir_Predefined_Functions;
- begin
- case Get_Identifier (Decl) is
- when Name_And =>
- Predefined := Iir_Predefined_Ieee_1164_Scalar_And;
- when Name_Nand =>
- Predefined := Iir_Predefined_Ieee_1164_Scalar_Nand;
- when Name_Or =>
- Predefined := Iir_Predefined_Ieee_1164_Scalar_Or;
- when Name_Nor =>
- Predefined := Iir_Predefined_Ieee_1164_Scalar_Nor;
- when Name_Xor =>
- Predefined := Iir_Predefined_Ieee_1164_Scalar_Xor;
- when Name_Xnor =>
- Predefined := Iir_Predefined_Ieee_1164_Scalar_Xnor;
- when others =>
- Predefined := Iir_Predefined_None;
- end case;
+ case Get_Identifier (Decl) is
+ when Name_Rising_Edge =>
+ Rising_Edge := Decl;
+ when Name_Falling_Edge =>
+ Falling_Edge := Decl;
+ when Name_To_Bitvector =>
+ Predefined := Iir_Predefined_Ieee_1164_To_Bitvector;
Set_Implicit_Definition (Decl, Predefined);
- end;
- elsif Is_Scalar_Function (Decl) then
- declare
- Predefined : Iir_Predefined_Functions;
- begin
- case Get_Identifier (Decl) is
- when Name_Not =>
- Predefined := Iir_Predefined_Ieee_1164_Scalar_Not;
- when Name_Op_Condition =>
- Predefined :=
- Iir_Predefined_Ieee_1164_Condition_Operator;
- when others =>
- Predefined := Iir_Predefined_None;
- end case;
- Set_Implicit_Definition (Decl, Predefined);
- end;
- elsif Is_Vector_Vector_Function (Decl) then
- declare
- Predefined : Iir_Predefined_Functions;
- begin
- case Get_Identifier (Decl) is
- when Name_And =>
- Predefined := Iir_Predefined_Ieee_1164_Vector_And;
- when Name_Nand =>
- Predefined := Iir_Predefined_Ieee_1164_Vector_Nand;
- when Name_Or =>
- Predefined := Iir_Predefined_Ieee_1164_Vector_Or;
- when Name_Nor =>
- Predefined := Iir_Predefined_Ieee_1164_Vector_Nor;
- when Name_Xor =>
- Predefined := Iir_Predefined_Ieee_1164_Vector_Xor;
- when Name_Xnor =>
- Predefined := Iir_Predefined_Ieee_1164_Vector_Xnor;
- when others =>
- Predefined := Iir_Predefined_None;
- end case;
- Set_Implicit_Definition (Decl, Predefined);
- end;
- elsif Is_Vector_Function (Decl) then
- declare
- Predefined : Iir_Predefined_Functions;
- begin
- case Get_Identifier (Decl) is
- when Name_Not =>
- Predefined := Iir_Predefined_Ieee_1164_Vector_Not;
- when Name_And =>
- Predefined :=
- Iir_Predefined_Ieee_1164_Vector_And_Reduce;
- when Name_Or =>
- Predefined :=
- Iir_Predefined_Ieee_1164_Vector_Or_Reduce;
- when others =>
- Predefined := Iir_Predefined_None;
- end case;
- Set_Implicit_Definition (Decl, Predefined);
- end;
- end if;
+ when others =>
+ if Is_Scalar_Scalar_Function (Decl) then
+ case Get_Identifier (Decl) is
+ when Name_And =>
+ Predefined := Iir_Predefined_Ieee_1164_Scalar_And;
+ when Name_Nand =>
+ Predefined := Iir_Predefined_Ieee_1164_Scalar_Nand;
+ when Name_Or =>
+ Predefined := Iir_Predefined_Ieee_1164_Scalar_Or;
+ when Name_Nor =>
+ Predefined := Iir_Predefined_Ieee_1164_Scalar_Nor;
+ when Name_Xor =>
+ Predefined := Iir_Predefined_Ieee_1164_Scalar_Xor;
+ when Name_Xnor =>
+ Predefined := Iir_Predefined_Ieee_1164_Scalar_Xnor;
+ when others =>
+ Predefined := Iir_Predefined_None;
+ end case;
+ Set_Implicit_Definition (Decl, Predefined);
+ elsif Is_Scalar_Function (Decl) then
+ case Get_Identifier (Decl) is
+ when Name_Not =>
+ Predefined := Iir_Predefined_Ieee_1164_Scalar_Not;
+ when Name_Op_Condition =>
+ Predefined :=
+ Iir_Predefined_Ieee_1164_Condition_Operator;
+ when others =>
+ Predefined := Iir_Predefined_None;
+ end case;
+ Set_Implicit_Definition (Decl, Predefined);
+ elsif Is_Vector_Vector_Function (Decl) then
+ case Get_Identifier (Decl) is
+ when Name_And =>
+ Predefined := Iir_Predefined_Ieee_1164_Vector_And;
+ when Name_Nand =>
+ Predefined := Iir_Predefined_Ieee_1164_Vector_Nand;
+ when Name_Or =>
+ Predefined := Iir_Predefined_Ieee_1164_Vector_Or;
+ when Name_Nor =>
+ Predefined := Iir_Predefined_Ieee_1164_Vector_Nor;
+ when Name_Xor =>
+ Predefined := Iir_Predefined_Ieee_1164_Vector_Xor;
+ when Name_Xnor =>
+ Predefined := Iir_Predefined_Ieee_1164_Vector_Xnor;
+ when others =>
+ Predefined := Iir_Predefined_None;
+ end case;
+ Set_Implicit_Definition (Decl, Predefined);
+ elsif Is_Vector_Function (Decl) then
+ case Get_Identifier (Decl) is
+ when Name_Not =>
+ Predefined := Iir_Predefined_Ieee_1164_Vector_Not;
+ when Name_And =>
+ Predefined :=
+ Iir_Predefined_Ieee_1164_Vector_And_Reduce;
+ when Name_Or =>
+ Predefined :=
+ Iir_Predefined_Ieee_1164_Vector_Or_Reduce;
+ when others =>
+ Predefined := Iir_Predefined_None;
+ end case;
+ Set_Implicit_Definition (Decl, Predefined);
+ end if;
+ end case;
end if;
end loop;
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index 6d0bca05a..d5ed8a8fc 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -4910,6 +4910,8 @@ package Vhdl.Nodes is
Iir_Predefined_Ieee_1164_Vector_Xnor,
Iir_Predefined_Ieee_1164_Vector_Not,
+ Iir_Predefined_Ieee_1164_To_Bitvector,
+
-- VHDL-2008 unary logic operators
Iir_Predefined_Ieee_1164_Vector_And_Reduce,
Iir_Predefined_Ieee_1164_Vector_Or_Reduce,