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* vhdl: recognize to_stdlogicvector. For #1628Tristan Gingold2021-02-041-0/+1
* update license headersumarcor2021-01-141-11/+9
* Typo fixes in Ada code.Patrick Lehmann2021-01-101-45/+45
* vhdl: fix reprint of vhdl08 array element constraints.Tristan Gingold2021-01-051-0/+17
* vhdl: recognize ieee.numeric_std_unsigned. For #1572Tristan Gingold2021-01-011-0/+3
* Rework initialization and finalization.Tristan Gingold2020-12-301-1/+4
* vhdl: handle locally static attributes on entity/architecture/configurationsTristan Gingold2020-12-081-0/+12
* vhdl: recognize logica vec/log and log/vec operators. For #1520Tristan Gingold2020-12-031-0/+14
* vhdl: analyze subprogram instantiations. WIP. For #1470Tristan Gingold2020-09-261-2/+8
* vhdl: parse subprogram instantiations. For #1470Tristan Gingold2020-09-241-0/+30
* vhdl: recognize find_leftmost/find_rightmost. For #1460Tristan Gingold2020-09-161-0/+6
* vhdl: recognize reduce operations from numeric_std.Tristan Gingold2020-09-141-0/+14
* vhdl: recognize more operators for std_logic_unsigned/signed.Tristan Gingold2020-08-071-0/+36
* vhdl: recognize more std_logic_arith operators.Tristan Gingold2020-08-071-0/+15
* vhdl: parse and analyze force/release signal assignment statements.Tristan Gingold2020-08-011-0/+44
* vhdl: adjust hanlding of guard signals for translate.Tristan Gingold2020-07-251-0/+2
* translate: improve support of unbounded records and arrays.Tristan Gingold2020-07-251-0/+3
* vhdl: replace base_type with parent_type in nodesTristan Gingold2020-07-221-38/+13
* vhdl: fix ownership for recors subtypes.Tristan Gingold2020-07-181-3/+7
* vhdl-nodes: reduce size of Iterator_Declaration.Tristan Gingold2020-07-011-3/+3
* vhdl-nodes: make Subtype_Indication Maybe_Ref. For #641Tristan Gingold2020-06-301-3/+14
* vhdl-nodes: add Open_Flag to all generic interfaces.Tristan Gingold2020-06-261-3/+10
* synth: handle std_logic_signed.conv_integer. For ghdl/ghdl-yosys-plugin#126Tristan Gingold2020-06-191-0/+2
* vhdl: decode to_x01 (from ieee.std_logic_1164)Tristan Gingold2020-06-191-0/+21
* vhdl: create default configuration for a vunit. Fix #1372Tristan Gingold2020-06-151-4/+10
* vhdl: analyze and synth concurrent statements in vunit. Fix #1366Tristan Gingold2020-06-121-0/+5
* Synthesis of PSL prev function.Tristan Gingold2020-06-021-7/+11
* vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662Tristan Gingold2020-06-021-0/+48
* synth: handle reduction operators. Fix #1342Tristan Gingold2020-05-271-2/+6
* vhdl-nodes: use a flag field for direction.Tristan Gingold2020-05-201-2/+2
* vhdl-nodes: Rename and move shift/rotate predefined functions. Fix #1325Tristan Gingold2020-05-191-9/+9
* synth: handle functional call to numeric_std binary operators. For #1313Tristan Gingold2020-05-161-24/+33
* vhdl: allow attribute specifications in protected types. For #1252Tristan Gingold2020-04-201-44/+48
* types: introduce Direction_Type, which replaces Iir_Direction.Tristan Gingold2020-04-201-8/+2
* vhdl: handling attribute specification in instantiations. Fix #1229Tristan Gingold2020-04-161-3/+3
* synth-oper: recognize more operations from std_logic_arith.Tristan Gingold2020-04-121-0/+26
* vhdl: recognize math_real.floor. For #1210Tristan Gingold2020-04-111-0/+1
* vhdl: recognize ext/sxt from std_logic_arith.Tristan Gingold2020-04-111-0/+3
* vhdl: recognize comparaison of std_logic_arith.Tristan Gingold2020-04-111-0/+54
* vhdl: add scalar_size. Size of scalar types is computed during analysis.Tristan Gingold2020-04-061-1/+24
* vhdl: recognize reduce functions in std_logic_misc.Tristan Gingold2020-03-281-1/+15
* vhdl: move get_subprogram_body_origin to vhdl-sem_inst.Tristan Gingold2020-03-241-0/+11
* synth: handle ieee.numeric_std.to_01Tristan Gingold2020-03-221-0/+3
* vhdl: recognize minimum/maximum in numeric_std. For #1168Tristan Gingold2020-03-211-0/+14
* synth: handle more operations from synsopsys packages.Tristan Gingold2020-03-141-8/+12
* vhdl: recognize more std_logic_arith operations.Tristan Gingold2020-03-131-1/+37
* vhdl-ieee-std_logic_arith: recognize more conversions.Tristan Gingold2020-03-111-1/+6
* vhdl: recognize mod/rem operators.Tristan Gingold2020-03-101-0/+14
* synthesis: add option --vendor-library= for synthesis.Tristan Gingold2020-03-101-0/+9
* vhdl: recognize conversion functions from std_logic_1164Tristan Gingold2020-02-181-0/+6
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