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vhdl-nodes.ads
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Author
Age
Files
Lines
*
vhdl: recognize to_stdlogicvector. For #1628
Tristan Gingold
2021-02-04
1
-0
/
+1
*
update license headers
umarcor
2021-01-14
1
-11
/
+9
*
Typo fixes in Ada code.
Patrick Lehmann
2021-01-10
1
-45
/
+45
*
vhdl: fix reprint of vhdl08 array element constraints.
Tristan Gingold
2021-01-05
1
-0
/
+17
*
vhdl: recognize ieee.numeric_std_unsigned. For #1572
Tristan Gingold
2021-01-01
1
-0
/
+3
*
Rework initialization and finalization.
Tristan Gingold
2020-12-30
1
-1
/
+4
*
vhdl: handle locally static attributes on entity/architecture/configurations
Tristan Gingold
2020-12-08
1
-0
/
+12
*
vhdl: recognize logica vec/log and log/vec operators. For #1520
Tristan Gingold
2020-12-03
1
-0
/
+14
*
vhdl: analyze subprogram instantiations. WIP. For #1470
Tristan Gingold
2020-09-26
1
-2
/
+8
*
vhdl: parse subprogram instantiations. For #1470
Tristan Gingold
2020-09-24
1
-0
/
+30
*
vhdl: recognize find_leftmost/find_rightmost. For #1460
Tristan Gingold
2020-09-16
1
-0
/
+6
*
vhdl: recognize reduce operations from numeric_std.
Tristan Gingold
2020-09-14
1
-0
/
+14
*
vhdl: recognize more operators for std_logic_unsigned/signed.
Tristan Gingold
2020-08-07
1
-0
/
+36
*
vhdl: recognize more std_logic_arith operators.
Tristan Gingold
2020-08-07
1
-0
/
+15
*
vhdl: parse and analyze force/release signal assignment statements.
Tristan Gingold
2020-08-01
1
-0
/
+44
*
vhdl: adjust hanlding of guard signals for translate.
Tristan Gingold
2020-07-25
1
-0
/
+2
*
translate: improve support of unbounded records and arrays.
Tristan Gingold
2020-07-25
1
-0
/
+3
*
vhdl: replace base_type with parent_type in nodes
Tristan Gingold
2020-07-22
1
-38
/
+13
*
vhdl: fix ownership for recors subtypes.
Tristan Gingold
2020-07-18
1
-3
/
+7
*
vhdl-nodes: reduce size of Iterator_Declaration.
Tristan Gingold
2020-07-01
1
-3
/
+3
*
vhdl-nodes: make Subtype_Indication Maybe_Ref. For #641
Tristan Gingold
2020-06-30
1
-3
/
+14
*
vhdl-nodes: add Open_Flag to all generic interfaces.
Tristan Gingold
2020-06-26
1
-3
/
+10
*
synth: handle std_logic_signed.conv_integer. For ghdl/ghdl-yosys-plugin#126
Tristan Gingold
2020-06-19
1
-0
/
+2
*
vhdl: decode to_x01 (from ieee.std_logic_1164)
Tristan Gingold
2020-06-19
1
-0
/
+21
*
vhdl: create default configuration for a vunit. Fix #1372
Tristan Gingold
2020-06-15
1
-4
/
+10
*
vhdl: analyze and synth concurrent statements in vunit. Fix #1366
Tristan Gingold
2020-06-12
1
-0
/
+5
*
Synthesis of PSL prev function.
Tristan Gingold
2020-06-02
1
-7
/
+11
*
vhdl: parse PSL prev/stable/rose/fell builtin calls. For #662
Tristan Gingold
2020-06-02
1
-0
/
+48
*
synth: handle reduction operators. Fix #1342
Tristan Gingold
2020-05-27
1
-2
/
+6
*
vhdl-nodes: use a flag field for direction.
Tristan Gingold
2020-05-20
1
-2
/
+2
*
vhdl-nodes: Rename and move shift/rotate predefined functions. Fix #1325
Tristan Gingold
2020-05-19
1
-9
/
+9
*
synth: handle functional call to numeric_std binary operators. For #1313
Tristan Gingold
2020-05-16
1
-24
/
+33
*
vhdl: allow attribute specifications in protected types. For #1252
Tristan Gingold
2020-04-20
1
-44
/
+48
*
types: introduce Direction_Type, which replaces Iir_Direction.
Tristan Gingold
2020-04-20
1
-8
/
+2
*
vhdl: handling attribute specification in instantiations. Fix #1229
Tristan Gingold
2020-04-16
1
-3
/
+3
*
synth-oper: recognize more operations from std_logic_arith.
Tristan Gingold
2020-04-12
1
-0
/
+26
*
vhdl: recognize math_real.floor. For #1210
Tristan Gingold
2020-04-11
1
-0
/
+1
*
vhdl: recognize ext/sxt from std_logic_arith.
Tristan Gingold
2020-04-11
1
-0
/
+3
*
vhdl: recognize comparaison of std_logic_arith.
Tristan Gingold
2020-04-11
1
-0
/
+54
*
vhdl: add scalar_size. Size of scalar types is computed during analysis.
Tristan Gingold
2020-04-06
1
-1
/
+24
*
vhdl: recognize reduce functions in std_logic_misc.
Tristan Gingold
2020-03-28
1
-1
/
+15
*
vhdl: move get_subprogram_body_origin to vhdl-sem_inst.
Tristan Gingold
2020-03-24
1
-0
/
+11
*
synth: handle ieee.numeric_std.to_01
Tristan Gingold
2020-03-22
1
-0
/
+3
*
vhdl: recognize minimum/maximum in numeric_std. For #1168
Tristan Gingold
2020-03-21
1
-0
/
+14
*
synth: handle more operations from synsopsys packages.
Tristan Gingold
2020-03-14
1
-8
/
+12
*
vhdl: recognize more std_logic_arith operations.
Tristan Gingold
2020-03-13
1
-1
/
+37
*
vhdl-ieee-std_logic_arith: recognize more conversions.
Tristan Gingold
2020-03-11
1
-1
/
+6
*
vhdl: recognize mod/rem operators.
Tristan Gingold
2020-03-10
1
-0
/
+14
*
synthesis: add option --vendor-library= for synthesis.
Tristan Gingold
2020-03-10
1
-0
/
+9
*
vhdl: recognize conversion functions from std_logic_1164
Tristan Gingold
2020-02-18
1
-0
/
+6
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