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| author | Tristan Gingold <tgingold@free.fr> | 2020-08-07 21:21:01 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-08-07 21:55:52 +0200 |
| commit | 228f27c826308da57887df34181f6f9bb14ca24f (patch) | |
| tree | 2f91904e59cfd555f9f5b44b11aadf8a309219d0 /src/vhdl/vhdl-nodes.ads | |
| parent | db12214157722a004cd951b40dd1bdf1449be200 (diff) | |
| download | ghdl-228f27c826308da57887df34181f6f9bb14ca24f.tar.gz ghdl-228f27c826308da57887df34181f6f9bb14ca24f.tar.bz2 ghdl-228f27c826308da57887df34181f6f9bb14ca24f.zip | |
vhdl: recognize more operators for std_logic_unsigned/signed.
Diffstat (limited to 'src/vhdl/vhdl-nodes.ads')
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index a08e12d97..eeaf86c72 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5824,6 +5824,8 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Log, Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Log_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Id_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Mul_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Slv, @@ -5852,6 +5854,9 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Unsigned_Conv_Integer, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Shl, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Shr, + -- Std_Logic_Signed (synopsys extension). Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int, @@ -5865,10 +5870,41 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Log, Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Log_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Id_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Neg_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Abs_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Mul_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Lt_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Lt_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Signed_Lt_Int_Slv, + + Iir_Predefined_Ieee_Std_Logic_Signed_Le_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Le_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Signed_Le_Int_Slv, + + Iir_Predefined_Ieee_Std_Logic_Signed_Gt_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Gt_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Signed_Gt_Int_Slv, + + Iir_Predefined_Ieee_Std_Logic_Signed_Ge_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Ge_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Signed_Ge_Int_Slv, + + Iir_Predefined_Ieee_Std_Logic_Signed_Eq_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Eq_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Signed_Eq_Int_Slv, + + Iir_Predefined_Ieee_Std_Logic_Signed_Ne_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Ne_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Signed_Ne_Int_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Conv_Integer, + Iir_Predefined_Ieee_Std_Logic_Signed_Shl, + Iir_Predefined_Ieee_Std_Logic_Signed_Shr, + -- std_logic_arith (synopsys extention). Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Uns, |