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| author | Tristan Gingold <tgingold@free.fr> | 2020-12-01 20:37:07 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-12-03 07:40:56 +0100 |
| commit | ad74ac7886532dd1a846712c92266158c8947589 (patch) | |
| tree | 95fe1ba5cc0a1691de3d63c03d87cdd06bef816c /src/vhdl/vhdl-nodes.ads | |
| parent | d8a74826a0bc2de58e8d3eeef64f72a51e6e4c9a (diff) | |
| download | ghdl-ad74ac7886532dd1a846712c92266158c8947589.tar.gz ghdl-ad74ac7886532dd1a846712c92266158c8947589.tar.bz2 ghdl-ad74ac7886532dd1a846712c92266158c8947589.zip | |
vhdl: recognize logica vec/log and log/vec operators. For #1520
Diffstat (limited to 'src/vhdl/vhdl-nodes.ads')
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index e6a9c3534..8e1d98c0b 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5595,6 +5595,20 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_Rising_Edge, Iir_Predefined_Ieee_1164_Falling_Edge, + -- VHDL-2008 vector/element logic operators + Iir_Predefined_Ieee_1164_And_Suv_Log, + Iir_Predefined_Ieee_1164_And_Log_Suv, + Iir_Predefined_Ieee_1164_Nand_Suv_Log, + Iir_Predefined_Ieee_1164_Nand_Log_Suv, + Iir_Predefined_Ieee_1164_Or_Suv_Log, + Iir_Predefined_Ieee_1164_Or_Log_Suv, + Iir_Predefined_Ieee_1164_Nor_Suv_Log, + Iir_Predefined_Ieee_1164_Nor_Log_Suv, + Iir_Predefined_Ieee_1164_Xor_Suv_Log, + Iir_Predefined_Ieee_1164_Xor_Log_Suv, + Iir_Predefined_Ieee_1164_Xnor_Suv_Log, + Iir_Predefined_Ieee_1164_Xnor_Log_Suv, + -- VHDL-2008 unary logic operators Iir_Predefined_Ieee_1164_And_Suv, Iir_Predefined_Ieee_1164_Nand_Suv, |