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| author | Tristan Gingold <tgingold@free.fr> | 2020-03-14 10:49:48 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-03-14 10:49:48 +0100 |
| commit | 543f1c62b4d3929d2cbabef02680cf8c5e2812ef (patch) | |
| tree | 75373dc0eca63faa0b504b714c97d82f37be351b /src/vhdl/vhdl-nodes.ads | |
| parent | ac815ad59528cfb6689a140065382e07e0d9318e (diff) | |
| download | ghdl-543f1c62b4d3929d2cbabef02680cf8c5e2812ef.tar.gz ghdl-543f1c62b4d3929d2cbabef02680cf8c5e2812ef.tar.bz2 ghdl-543f1c62b4d3929d2cbabef02680cf8c5e2812ef.zip | |
synth: handle more operations from synsopsys packages.
Diffstat (limited to 'src/vhdl/vhdl-nodes.ads')
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 56c231301..8be86f9dd 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5689,14 +5689,16 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Int_Slv, - Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl, - Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Sl_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Log, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Log_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Int_Slv, - Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Sl, - Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Sl_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Log, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Log_Slv, + + Iir_Predefined_Ieee_Std_Logic_Unsigned_Mul_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Int, @@ -5728,14 +5730,16 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Signed_Add_Int_Slv, - Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Sl, - Iir_Predefined_Ieee_Std_Logic_Signed_Add_Sl_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Log, + Iir_Predefined_Ieee_Std_Logic_Signed_Add_Log_Slv, Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Int_Slv, - Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Sl, - Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Sl_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Log, + Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Log_Slv, + + Iir_Predefined_Ieee_Std_Logic_Signed_Mul_Slv_Slv, -- std_logic_arith (synopsys extention). Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int, |