| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | vhdl: introduce iir_kind_association_element_by_name | Tristan Gingold | 2021-08-06 | 1 | -1/+1 |
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| * | update license headers | umarcor | 2021-01-14 | 1 | -11/+9 |
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| * | src/vhd: remove use of chapter sign in comment to have on ASCII characters | Tristan Gingold | 2021-01-09 | 1 | -17/+17 |
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| * | vhdl: improve support of AMS-vhdl (array and record natures, source quantities) | Tristan Gingold | 2019-12-28 | 1 | -0/+2 |
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| * | Add support for PSL assumptions, used in formal verification (#880) | Pepijn de Vos | 2019-08-07 | 1 | -1/+2 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | * vhdl: make the parser understand PSL assume * assume does not actually have report according to the spec. Just a property. * add SPL assume to semantic analysis * canonicalise PSL assume * add assume to annotations * add PSL assume to simulation code * statement -> directive * add assume to translation files * update ticked24 testcase * correctly parse assume * add assume testcase * refactor chunk of duplicated code | ||||
| * | simul-elaboration: rewrite assertion. | Tristan Gingold | 2019-07-13 | 1 | -3/+3 |
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| * | vhdl simul-elaboration: minor rewrite. | Tristan Gingold | 2019-07-08 | 1 | -3/+1 |
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| * | vhdl: rename Cover_Statement to Cover_Directive. | Tristan Gingold | 2019-07-04 | 1 | -1/+1 |
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| * | vhdl: decouple annotations from environments. | Tristan Gingold | 2019-06-19 | 1 | -16/+22 |
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| * | vhdl/simulate: fix regression wrt package instances. | Tristan Gingold | 2019-06-12 | 1 | -3/+5 |
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| * | synth: handle integer +/- for constants. | Tristan Gingold | 2019-06-08 | 1 | -1/+2 |
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| * | vhdl/simulate: ignore some constructs for synthesis. | Tristan Gingold | 2019-05-23 | 1 | -1/+2 |
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| * | Add simple_IO - to be used instead of Text_IO. | Tristan Gingold | 2019-05-19 | 1 | -10/+10 |
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| * | vhdl: decouple errorouts a bit more. | Tristan Gingold | 2019-05-10 | 1 | -2/+2 |
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| * | vhdl: extract vhdl.errors from errorout. | Tristan Gingold | 2019-05-08 | 1 | -0/+1 |
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| * | vhdl-nodes_utils: renaming. | Tristan Gingold | 2019-05-07 | 1 | -2/+2 |
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| * | vhdl: renames iir_chains to vhdl.nodes_utils. Remove iir_chain_handling. | Tristan Gingold | 2019-05-06 | 1 | -1/+1 |
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| * | vhdl: move iirs_utils to vhdl.utils | Tristan Gingold | 2019-05-06 | 1 | -1/+1 |
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| * | vhdl: move evaluation to vhdl child. | Tristan Gingold | 2019-05-05 | 1 | -2/+2 |
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| * | vhdl: move sem* packages to vhdl children. | Tristan Gingold | 2019-05-05 | 1 | -1/+1 |
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| * | simul: do not reverse the list twice; renaming. | Tristan Gingold | 2019-04-16 | 1 | -24/+16 |
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| * | simul: adjust after previous changes. | Tristan Gingold | 2018-11-15 | 1 | -2/+3 |
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| * | Improve doc, fix English typo. | Tristan Gingold | 2018-09-23 | 1 | -5/+6 |
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| * | simul: remove ports_map from instances (not used). | Tristan Gingold | 2018-01-02 | 1 | -5/+0 |
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| * | simul: Add subprogram body in frames. | Tristan Gingold | 2017-12-21 | 1 | -2/+8 |
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| * | simul: handle psl endpoints (and adjust issue45). | Tristan Gingold | 2017-12-21 | 1 | -3/+13 |
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| * | simul: create initial driver value. | Tristan Gingold | 2017-12-21 | 1 | -8/+15 |
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| * | simul: minor refactoring. | Tristan Gingold | 2017-12-21 | 1 | -4/+2 |
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| * | simul-elaboration: handle unbounded records. | Tristan Gingold | 2017-12-11 | 1 | -1/+1 |
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| * | simul: Check range of the result of concat operator. | Tristan Gingold | 2017-12-11 | 1 | -5/+1 |
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| * | simul: handle optional body for package instantiation. | Tristan Gingold | 2017-12-07 | 1 | -2/+5 |
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| * | simul: handle interface type. | Tristan Gingold | 2017-12-07 | 1 | -2/+4 |
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| * | simul: handle generic-mapped packages. | Tristan Gingold | 2017-12-07 | 1 | -4/+11 |
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| * | simul: handle nested package instantiation. | Tristan Gingold | 2017-12-07 | 1 | -1/+2 |
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| * | simul: fix execution of actual expression. | Tristan Gingold | 2017-12-06 | 1 | -3/+4 |
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| * | simul: remove Current_Component (unused). | Tristan Gingold | 2017-12-06 | 1 | -9/+3 |
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| * | simul: fix elaboration check for package. | Tristan Gingold | 2017-12-05 | 1 | -1/+5 |
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| * | simul: psl default clock, unaffected waveform. | Tristan Gingold | 2017-12-05 | 1 | -0/+3 |
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| * | simul: handle interface subprogram. | Tristan Gingold | 2017-12-05 | 1 | -8/+19 |
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| * | simul: handle package interface, remove iir_value_environment. | Tristan Gingold | 2017-12-05 | 1 | -7/+4 |
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| * | simul: handle instantiated package. | Tristan Gingold | 2017-12-05 | 1 | -1/+6 |
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| * | simul: add support for case generate statetement. | Tristan Gingold | 2017-12-04 | 1 | -9/+43 |
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| * | simul: support nested packages. | Tristan Gingold | 2017-12-04 | 1 | -4/+12 |
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| * | simul: WIP for nested packages. | Tristan Gingold | 2017-12-04 | 1 | -1/+1 |
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| * | simul: add iir_value_instance, remove package_instances. | Tristan Gingold | 2017-12-03 | 1 | -20/+38 |
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| * | simul: add global_info. | Tristan Gingold | 2017-12-03 | 1 | -8/+7 |
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| * | simul: refactoring: scope is now the corresponding sim_info. | Tristan Gingold | 2017-12-03 | 1 | -3/+4 |
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| * | Create the simul.ads package (for a namespace). | Tristan Gingold | 2017-11-24 | 1 | -0/+2979 |
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