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| author | Tristan Gingold <tgingold@free.fr> | 2017-12-11 18:41:42 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2017-12-11 18:41:42 +0100 |
| commit | ce3659abec1037f8dc4ad62eecdaba08884ce348 (patch) | |
| tree | 3189774f85512fcb16523ef890b466b77ab33a88 /src/vhdl/simulate/simul-elaboration.adb | |
| parent | 1451879337efac06519bbcb080729172d03d4a58 (diff) | |
| download | ghdl-ce3659abec1037f8dc4ad62eecdaba08884ce348.tar.gz ghdl-ce3659abec1037f8dc4ad62eecdaba08884ce348.tar.bz2 ghdl-ce3659abec1037f8dc4ad62eecdaba08884ce348.zip | |
simul: Check range of the result of concat operator.
Diffstat (limited to 'src/vhdl/simulate/simul-elaboration.adb')
| -rw-r--r-- | src/vhdl/simulate/simul-elaboration.adb | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb index 0eb6047c1..a6dc61ebf 100644 --- a/src/vhdl/simulate/simul-elaboration.adb +++ b/src/vhdl/simulate/simul-elaboration.adb @@ -848,11 +848,7 @@ package body Simul.Elaboration is (Execute_Expression (Instance, Get_Left_Limit (Rc)), Execute_Expression (Instance, Get_Right_Limit (Rc)), Get_Direction (Rc)); - -- Check constraints. - if not Is_Null_Range (Val) then - Check_Constraints (Instance, Val.Left, Get_Type (Rc), Rc); - Check_Constraints (Instance, Val.Right, Get_Type (Rc), Rc); - end if; + Check_Range_Constraints (Instance, Val, Rc, Rc); Instance.Objects (Range_Info.Slot) := Unshare (Val, Instance_Pool); end Elaborate_Range_Expression; |