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* vhdl: introduce iir_kind_association_element_by_nameTristan Gingold2021-08-061-1/+1
* update license headersumarcor2021-01-141-11/+9
* src/vhd: remove use of chapter sign in comment to have on ASCII charactersTristan Gingold2021-01-091-17/+17
* vhdl: improve support of AMS-vhdl (array and record natures, source quantities)Tristan Gingold2019-12-281-0/+2
* Add support for PSL assumptions, used in formal verification (#880)Pepijn de Vos2019-08-071-1/+2
* simul-elaboration: rewrite assertion.Tristan Gingold2019-07-131-3/+3
* vhdl simul-elaboration: minor rewrite.Tristan Gingold2019-07-081-3/+1
* vhdl: rename Cover_Statement to Cover_Directive.Tristan Gingold2019-07-041-1/+1
* vhdl: decouple annotations from environments.Tristan Gingold2019-06-191-16/+22
* vhdl/simulate: fix regression wrt package instances.Tristan Gingold2019-06-121-3/+5
* synth: handle integer +/- for constants.Tristan Gingold2019-06-081-1/+2
* vhdl/simulate: ignore some constructs for synthesis.Tristan Gingold2019-05-231-1/+2
* Add simple_IO - to be used instead of Text_IO.Tristan Gingold2019-05-191-10/+10
* vhdl: decouple errorouts a bit more.Tristan Gingold2019-05-101-2/+2
* vhdl: extract vhdl.errors from errorout.Tristan Gingold2019-05-081-0/+1
* vhdl-nodes_utils: renaming.Tristan Gingold2019-05-071-2/+2
* vhdl: renames iir_chains to vhdl.nodes_utils. Remove iir_chain_handling.Tristan Gingold2019-05-061-1/+1
* vhdl: move iirs_utils to vhdl.utilsTristan Gingold2019-05-061-1/+1
* vhdl: move evaluation to vhdl child.Tristan Gingold2019-05-051-2/+2
* vhdl: move sem* packages to vhdl children.Tristan Gingold2019-05-051-1/+1
* simul: do not reverse the list twice; renaming.Tristan Gingold2019-04-161-24/+16
* simul: adjust after previous changes.Tristan Gingold2018-11-151-2/+3
* Improve doc, fix English typo.Tristan Gingold2018-09-231-5/+6
* simul: remove ports_map from instances (not used).Tristan Gingold2018-01-021-5/+0
* simul: Add subprogram body in frames.Tristan Gingold2017-12-211-2/+8
* simul: handle psl endpoints (and adjust issue45).Tristan Gingold2017-12-211-3/+13
* simul: create initial driver value.Tristan Gingold2017-12-211-8/+15
* simul: minor refactoring.Tristan Gingold2017-12-211-4/+2
* simul-elaboration: handle unbounded records.Tristan Gingold2017-12-111-1/+1
* simul: Check range of the result of concat operator.Tristan Gingold2017-12-111-5/+1
* simul: handle optional body for package instantiation.Tristan Gingold2017-12-071-2/+5
* simul: handle interface type.Tristan Gingold2017-12-071-2/+4
* simul: handle generic-mapped packages.Tristan Gingold2017-12-071-4/+11
* simul: handle nested package instantiation.Tristan Gingold2017-12-071-1/+2
* simul: fix execution of actual expression.Tristan Gingold2017-12-061-3/+4
* simul: remove Current_Component (unused).Tristan Gingold2017-12-061-9/+3
* simul: fix elaboration check for package.Tristan Gingold2017-12-051-1/+5
* simul: psl default clock, unaffected waveform.Tristan Gingold2017-12-051-0/+3
* simul: handle interface subprogram.Tristan Gingold2017-12-051-8/+19
* simul: handle package interface, remove iir_value_environment.Tristan Gingold2017-12-051-7/+4
* simul: handle instantiated package.Tristan Gingold2017-12-051-1/+6
* simul: add support for case generate statetement.Tristan Gingold2017-12-041-9/+43
* simul: support nested packages.Tristan Gingold2017-12-041-4/+12
* simul: WIP for nested packages.Tristan Gingold2017-12-041-1/+1
* simul: add iir_value_instance, remove package_instances.Tristan Gingold2017-12-031-20/+38
* simul: add global_info.Tristan Gingold2017-12-031-8/+7
* simul: refactoring: scope is now the corresponding sim_info.Tristan Gingold2017-12-031-3/+4
* Create the simul.ads package (for a namespace).Tristan Gingold2017-11-241-0/+2979
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