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authorTristan Gingold <tgingold@free.fr>2019-05-05 08:13:25 +0200
committerTristan Gingold <tgingold@free.fr>2019-05-05 13:55:18 +0200
commitec5cdde54b8b59e6bb0ecdd05938adc8f40e8521 (patch)
treedcaf93b4dc1ddda8b069d01f2e9dd8d06124a77d /src/vhdl/simulate/simul-elaboration.adb
parent79d521d70cc07e0afa6eb88632ca84aeadd3c62a (diff)
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vhdl: move evaluation to vhdl child.
Diffstat (limited to 'src/vhdl/simulate/simul-elaboration.adb')
-rw-r--r--src/vhdl/simulate/simul-elaboration.adb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb
index 3addbef91..a961aeeae 100644
--- a/src/vhdl/simulate/simul-elaboration.adb
+++ b/src/vhdl/simulate/simul-elaboration.adb
@@ -19,7 +19,7 @@
with Ada.Text_IO;
with Str_Table;
with Errorout; use Errorout;
-with Evaluation;
+with Vhdl.Evaluation;
with Simul.Execution; use Simul.Execution;
with Iirs_Utils; use Iirs_Utils;
with Libraries;
@@ -2861,7 +2861,7 @@ package body Simul.Elaboration is
function Override_Generic (Formal : Iir; Str : String) return Iir
is
- use Evaluation;
+ use Vhdl.Evaluation;
Formal_Type : constant Iir := Get_Type (Formal);
Formal_Btype : constant Iir := Get_Base_Type (Formal_Type);
Res : Iir;