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* synth-vhdl_stmts: add location on AddidxTristan Gingold2021-06-211-0/+2
* synth-environment: early transformation of dyn_insert to dyn_insert_enTristan Gingold2021-06-214-25/+59
* synth-vhdl_stmts: merge static extract before dyn_extract.Tristan Gingold2021-06-211-4/+2
* synth-vhdl_expr: adjust width of memidx for indexed names.Tristan Gingold2021-06-211-1/+1
* synth: add a gate on an optimization to simplify memory handling.Tristan Gingold2021-06-172-67/+38
* netlists-memories: strengthen dyn_extract mux reduction. Fix #1781Tristan Gingold2021-06-162-1/+52
* synth: minor fixesTristan Gingold2021-06-152-9/+8
* netlists-memories: avoid a crash on uninitialized ROM.Tristan Gingold2021-05-241-1/+9
* netlists-disp_verilog: fix display of constantsTristan Gingold2021-05-071-10/+20
* synth-environment: add Set/Get_Kind, Wire_UnsetTristan Gingold2021-05-072-1/+26
* netlists-cleanup: do not remove self-assigned output gateTristan Gingold2021-05-071-23/+30
* netlists-disp_verilog.adb: handle memidx, dyn_insert, dyn_extract.Tristan Gingold2021-05-041-74/+14
* synth: add verilog outputTristan Gingold2021-04-282-0/+1417
* synth: file renaming for decls, expr, insts and stmts.Tristan Gingold2021-04-2814-45/+49
* synth: use a generic version of synth-environment.Tristan Gingold2021-04-2718-363/+479
* synth-insts.adb: avoid a crash after an error during instantiation. Fix #1734Tristan Gingold2021-04-232-1/+9
* synth-vhdl_oper.adb: handle resize uns/uns. For #1731Tristan Gingold2021-04-211-0/+12
* synth-vhdl_oper.adb: adjust previous patch and testTristan Gingold2021-04-211-1/+12
* synth-vhdl_oper.adb: handle resize sgn/sgn. Fix #1731Tristan Gingold2021-04-211-0/+1
* synth: extract synth-memtype from synth-objtypesTristan Gingold2021-04-2115-124/+193
* synth: renaming (synth-heap -> synth-vhdl_heap)Tristan Gingold2021-04-165-11/+11
* synth: renaming (synth-static_proc -> synth-vhdl_static_proc)Tristan Gingold2021-04-163-6/+6
* synth: refactoring (synth.files_operations -> synth.vhdl_files)Tristan Gingold2021-04-166-11/+11
* synth: renaming (synth.oper -> synth.vhdl_oper)Tristan Gingold2021-04-164-11/+11
* synth: refactoring (synth.aggr -> synth.vhdl_aggr)Tristan Gingold2021-04-163-7/+7
* synth: rename synth-context to synth-vhdl_contextTristan Gingold2021-04-1615-23/+23
* synth: avoid crash in case of non-elaboratable generic.Tristan Gingold2021-04-152-4/+10
* vhdl and libraries: add support for binding to a foreign moduleTristan Gingold2021-04-051-0/+5
* netlists-disp_vhdl: do not display edge net when not needed. Fix #1703Tristan Gingold2021-03-293-25/+49
* synth: expand ports for record. Fix #1675Tristan Gingold2021-03-273-65/+270
* netlists-dump: also dump attributesTristan Gingold2021-03-173-74/+168
* synth: handle loc attribute (for ports). Fix #1682Tristan Gingold2021-03-172-1/+5
* netlists: do not remove net gates that have an attributeTristan Gingold2021-03-173-25/+36
* synth-expr.adb: add commentsTristan Gingold2021-03-141-0/+5
* synth-expr.adb: handle const right in synth_short_circuit. Fix #1685Tristan Gingold2021-03-141-0/+6
* synth-oper: handle const for numeric_std.match Fix #1679Tristan Gingold2021-03-131-0/+1
* synth-expr: allow non-simple name for FF clocks. Fix #1681Tristan Gingold2021-03-131-12/+17
* synth: handle attributes of length 0. Fix #1680Tristan Gingold2021-03-132-3/+6
* Include directory structure proposal.Michał Kruszewski2021-03-072-1/+1
* synth: handle pow and arctan from ieee.math_real. Fix #1665Tristan Gingold2021-02-271-0/+16
* synth-stmts: handle attributes in block and generate statements. Fix #1658Tristan Gingold2021-02-211-0/+5
* synth-expr: compute signess for range array attributes. Fix #1645Tristan Gingold2021-02-123-17/+9
* netlists-folds: add commentsTristan Gingold2021-02-091-0/+4
* Add support for PSL onehot/onehot0 functions (#1633)T. Meissner2021-02-091-0/+92
* update license headersumarcor2021-02-0590-461/+282
* synth: handle to_stdlogicvector. For #1628Tristan Gingold2021-02-041-1/+2
* std_names: add gclk. For #1610Tristan Gingold2021-01-252-0/+9
* synth-insts: apply attributes to entities and architectures. Fix #1609Tristan Gingold2021-01-172-0/+12
* synth-stmts: add location on formal attribute cellsTristan Gingold2021-01-171-0/+1
* synth-expr: handle string literals in port associations. Fix #1596Tristan Gingold2021-01-161-0/+6
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