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authorTristan Gingold <tgingold@free.fr>2021-06-21 07:58:55 +0200
committerTristan Gingold <tgingold@free.fr>2021-06-21 08:07:14 +0200
commit1f1d8f56254af4b13c539a336e54e917e40fa3d6 (patch)
tree82843d8ccddaf33fe060d7c7b01d9d2be611aaae /src/synth
parent09e1764ea6dcf08aa77f8b6f5115caca9de44057 (diff)
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synth-vhdl_stmts: add location on Addidx
Diffstat (limited to 'src/synth')
-rw-r--r--src/synth/synth-vhdl_stmts.adb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb
index dbb6b10a9..544b4ebf4 100644
--- a/src/synth/synth-vhdl_stmts.adb
+++ b/src/synth/synth-vhdl_stmts.adb
@@ -166,6 +166,7 @@ package body Synth.Vhdl_Stmts is
Dest_Dyn.Voff := Build_Addidx
(Get_Build (Syn_Inst), Dest_Dyn.Voff, Voff);
+ Set_Location (Dest_Dyn.Voff, Pfx);
end if;
end if;
@@ -228,6 +229,7 @@ package body Synth.Vhdl_Stmts is
Dest_Dyn.Voff := Build_Addidx
(Get_Build (Syn_Inst), Dest_Dyn.Voff, Sl_Voff);
+ Set_Location (Dest_Dyn.Voff, Pfx);
end if;
Dest_Typ := Create_Slice_Type (Res_Bnd.Len, El_Typ);
end if;