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| author | Tristan Gingold <tgingold@free.fr> | 2021-04-21 20:38:38 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-04-21 20:38:38 +0200 |
| commit | c9c04ce167a18eb0bf54dbef71244c892e8c04ec (patch) | |
| tree | 540f96500403bde4e337da1d12b75380f798ef90 /src/synth | |
| parent | 45f80d929899d8c16754736eb5cecd508f3ec85b (diff) | |
| download | ghdl-c9c04ce167a18eb0bf54dbef71244c892e8c04ec.tar.gz ghdl-c9c04ce167a18eb0bf54dbef71244c892e8c04ec.tar.bz2 ghdl-c9c04ce167a18eb0bf54dbef71244c892e8c04ec.zip | |
synth-vhdl_oper.adb: adjust previous patch and test
resize with two signed parameters extract the size of the second parameter
to resize the first one.
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index f741d7fc7..26a886edf 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -1961,7 +1961,6 @@ package body Synth.Vhdl_Oper is Create_Vec_Type_By_Length (W, Logic_Type)); end; when Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Nat - | Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Sxt => @@ -1978,6 +1977,18 @@ package body Synth.Vhdl_Oper is W, Get_Location (Expr)), Create_Vec_Type_By_Length (W, Logic_Type)); end; + when Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Sgn => + declare + B : Bound_Type; + W : Width; + begin + B := Get_Array_Bound (R.Typ, 1); + W := B.Len; + return Create_Value_Net + (Build2_Sresize (Ctxt, Get_Net (Ctxt, L), + W, Get_Location (Expr)), + Create_Vec_Type_By_Length (W, Logic_Type)); + end; when Iir_Predefined_Ieee_Numeric_Std_Shf_Left_Uns_Nat | Iir_Predefined_Ieee_Numeric_Std_Shf_Left_Sgn_Nat | Iir_Predefined_Ieee_Std_Logic_Arith_Shl_Uns |