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* synth-vhdl_stmts: fix crash on nested if-generate statement in vunits.Tristan Gingold2021-09-111-2/+5
* vhdl: allow constants in vunit declarations. Fix #1856Tristan Gingold2021-09-081-0/+2
* netlists-cleanup: avoid crash when keep attribute value is a stringTristan Gingold2021-09-071-2/+39
* synth-vhdl_stmts.adb: do not expect configuration for vunit.Tristan Gingold2021-09-011-3/+3
* synth: handle PSL async_abort and sync_abort. For #1654Tristan Gingold2021-08-313-10/+44
* synth-vhdl_stmts: fix a crash on never triggered PSL assertion.Tristan Gingold2021-08-291-0/+6
* synth: improve result of is_positiveTristan Gingold2021-08-294-10/+15
* netlists-inference: improve location for dff.Tristan Gingold2021-08-291-1/+1
* synth: factorize code to create base instanceTristan Gingold2021-08-287-57/+104
* synthesis.adb: abstract instance_passesTristan Gingold2021-08-283-23/+34
* synth-environment: add subprograms for signals (preliminary work)Tristan Gingold2021-08-282-5/+110
* synth-memtype: export conversion functionsTristan Gingold2021-08-282-7/+9
* synth: add build2_concat2 and use it for vhdl concat.Tristan Gingold2021-08-283-4/+18
* ghdlsynth: add debug option for elaborationTristan Gingold2021-08-281-0/+3
* synth-vhdl_decls.adb: add commentsTristan Gingold2021-08-281-0/+4
* netlists-disp_verilog: handle initial value for idff and isignalTristan Gingold2021-08-281-8/+18
* synth: do not remove signals with a keep attribute.Tristan Gingold2021-08-272-1/+31
* netlists-disp_verilog: fix handling of unconnected portTristan Gingold2021-08-261-3/+1
* synth: reuse signal name while creating memories. Fix #1838Tristan Gingold2021-08-255-20/+34
* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-244-19/+0
* vhdl: introduce iir_kind_association_element_by_nameTristan Gingold2021-08-061-3/+4
* synth: minor renaming in netlists-memoriesTristan Gingold2021-06-303-10/+11
* synth-vhdl_context.adb(Is_Full): consider fractional words.Tristan Gingold2021-06-231-2/+16
* synth-vhdl_stmts: add location on AddidxTristan Gingold2021-06-211-0/+2
* synth-environment: early transformation of dyn_insert to dyn_insert_enTristan Gingold2021-06-214-25/+59
* synth-vhdl_stmts: merge static extract before dyn_extract.Tristan Gingold2021-06-211-4/+2
* synth-vhdl_expr: adjust width of memidx for indexed names.Tristan Gingold2021-06-211-1/+1
* synth: add a gate on an optimization to simplify memory handling.Tristan Gingold2021-06-172-67/+38
* netlists-memories: strengthen dyn_extract mux reduction. Fix #1781Tristan Gingold2021-06-162-1/+52
* synth: minor fixesTristan Gingold2021-06-152-9/+8
* netlists-memories: avoid a crash on uninitialized ROM.Tristan Gingold2021-05-241-1/+9
* netlists-disp_verilog: fix display of constantsTristan Gingold2021-05-071-10/+20
* synth-environment: add Set/Get_Kind, Wire_UnsetTristan Gingold2021-05-072-1/+26
* netlists-cleanup: do not remove self-assigned output gateTristan Gingold2021-05-071-23/+30
* netlists-disp_verilog.adb: handle memidx, dyn_insert, dyn_extract.Tristan Gingold2021-05-041-74/+14
* synth: add verilog outputTristan Gingold2021-04-282-0/+1417
* synth: file renaming for decls, expr, insts and stmts.Tristan Gingold2021-04-2814-45/+49
* synth: use a generic version of synth-environment.Tristan Gingold2021-04-2718-363/+479
* synth-insts.adb: avoid a crash after an error during instantiation. Fix #1734Tristan Gingold2021-04-232-1/+9
* synth-vhdl_oper.adb: handle resize uns/uns. For #1731Tristan Gingold2021-04-211-0/+12
* synth-vhdl_oper.adb: adjust previous patch and testTristan Gingold2021-04-211-1/+12
* synth-vhdl_oper.adb: handle resize sgn/sgn. Fix #1731Tristan Gingold2021-04-211-0/+1
* synth: extract synth-memtype from synth-objtypesTristan Gingold2021-04-2115-124/+193
* synth: renaming (synth-heap -> synth-vhdl_heap)Tristan Gingold2021-04-165-11/+11
* synth: renaming (synth-static_proc -> synth-vhdl_static_proc)Tristan Gingold2021-04-163-6/+6
* synth: refactoring (synth.files_operations -> synth.vhdl_files)Tristan Gingold2021-04-166-11/+11
* synth: renaming (synth.oper -> synth.vhdl_oper)Tristan Gingold2021-04-164-11/+11
* synth: refactoring (synth.aggr -> synth.vhdl_aggr)Tristan Gingold2021-04-163-7/+7
* synth: rename synth-context to synth-vhdl_contextTristan Gingold2021-04-1615-23/+23
* synth: avoid crash in case of non-elaboratable generic.Tristan Gingold2021-04-152-4/+10
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