iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth: improve support of vhdl08. Fix #882	Tristan Gingold	2019-08-05	1	-4/+13
*	synth: add asserts in synth-values	Tristan Gingold	2019-08-05	1	-0/+5
*	synth: handle subtype conversions.	Tristan Gingold	2019-08-05	5	-73/+154
*	synth: handle signed conversions in disp_vhdl.	Tristan Gingold	2019-08-05	1	-2/+6
*	synth: preliminary support of integer literals.	Tristan Gingold	2019-08-02	2	-18/+67
*	synth: add a debug procedure.	Tristan Gingold	2019-08-02	2	-0/+22
*	synth: improve error message for multiple assignments.	Tristan Gingold	2019-08-02	1	-4/+20
*	synth: handle signed integer comparisons (#878)	Pepijn de Vos	2019-08-01	3	-0/+43
*	synth: handle partial assignments in a process (WIP).	Tristan Gingold	2019-08-01	1	-18/+75
*	synth: refactoring in inference/environment.	Tristan Gingold	2019-08-01	3	-7/+13
*	synth: refactor inference, add comment, strengthen check.	Tristan Gingold	2019-08-01	4	-31/+62
*	synth: refactoring in synth-inference.	Tristan Gingold	2019-07-31	1	-129/+137
*	synth: add location on monadic operators.	Tristan Gingold	2019-07-31	1	-7/+10
*	synth: regenerate ghdlsynth_gates.h	Tristan Gingold	2019-07-31	1	-3/+4
*	synth: fix a crash in instantiation.	Tristan Gingold	2019-07-31	2	-8/+9
*	synth: slightly improve output for indexes.	Tristan Gingold	2019-07-30	1	-3/+7
*	synth: adjust output for dyn_insert, add dpram2 test.	Tristan Gingold	2019-07-30	1	-2/+2
*	synth: fixes for indexed names.	Tristan Gingold	2019-07-30	3	-3/+13
*	synth: rework indexed names.	Tristan Gingold	2019-07-30	4	-101/+106
*	synth: handle more conversions in disp_vhdl	Tristan Gingold	2019-07-29	1	-1/+44
*	synth: add support for memories.	Tristan Gingold	2019-07-29	14	-152/+443
*	synth: remove extract_bound (trivial).	Tristan Gingold	2019-07-28	5	-15/+6
*	synth: unconstrained arrays.	Tristan Gingold	2019-07-28	4	-17/+68
*	synth: preliminary support of dynamic indexing.	Tristan Gingold	2019-07-28	11	-693/+886
*	synth: rework range.	Tristan Gingold	2019-07-26	5	-48/+52
*	synth: preliminary support of integer subtypes.	Tristan Gingold	2019-07-26	8	-42/+68
*	synth: handle array aggregate.	Tristan Gingold	2019-07-26	2	-27/+32
*	synth: handle bit.	Tristan Gingold	2019-07-25	3	-4/+11
*	synth: array inequality, integer in choices.	Tristan Gingold	2019-07-25	2	-0/+11
*	vhdl+synth: recognize /= to std_logic_unsigned.	Tristan Gingold	2019-07-25	1	-0/+3
*	synth: save and display locations for instances.	Tristan Gingold	2019-07-25	8	-66/+247
*	synth: fix incorrect slice in disp_vhdl for Insert.	Tristan Gingold	2019-07-25	1	-6/+1
*	synth: fix bad ordering in case statement.	Tristan Gingold	2019-07-24	1	-2/+3
*	synth: do not consider (unrecognized) ieee functions as user functions.	Tristan Gingold	2019-07-24	1	-0/+19
*	synth: handle resize.	Tristan Gingold	2019-07-24	1	-0/+15
*	synth: handle record type declarations.	Tristan Gingold	2019-07-24	1	-1/+11
*	synth: fix slice/indexed assignment that partially override previous assign.	Tristan Gingold	2019-07-23	1	-5/+8
*	synth: add more operators.	Tristan Gingold	2019-07-23	1	-1/+34
*	synth: fix to_unsigned.	Tristan Gingold	2019-07-23	1	-2/+2
*	synth: use original entity to display netlist.	Tristan Gingold	2019-07-23	6	-20/+304
*	synth: remove bounds (unused) for ports.	Tristan Gingold	2019-07-22	4	-13/+4
*	synth: minor refactoring in netlists.disp_vhdl	Tristan Gingold	2019-07-22	2	-47/+54
*	synth: rework names.	Tristan Gingold	2019-07-22	6	-24/+25
*	add port width utility function for yosys (#876)	Pepijn de Vos	2019-07-21	4	-0/+18
*	synth: improve output (id_extract).	Tristan Gingold	2019-07-20	1	-6/+12
*	synth: improve output (for id_insert).	Tristan Gingold	2019-07-20	1	-11/+18
*	synth: add support for concurrent selected signal assignment.	Tristan Gingold	2019-07-20	1	-2/+138
*	synth: support index of a constant.	Tristan Gingold	2019-07-20	1	-0/+4
*	synth: initial support for for-generate statement.	Tristan Gingold	2019-07-20	2	-29/+89
*	synth: add and merge phi within a function.	Tristan Gingold	2019-07-20	1	-0/+5