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synth
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Author
Age
Files
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*
synth-vhdl_eval: handle std_logic_misc reduce functions
Tristan Gingold
2022-10-19
1
-0
/
+27
*
synth-vhdl_oper: handle xor/nand/nor/xnor reduce from std_logic_misc
Tristan Gingold
2022-10-19
1
-16
/
+34
*
synth-vhdl_oper: handle and_reduce. Fix #2224
Tristan Gingold
2022-10-19
1
-1
/
+10
*
synth: extract elab-vhdl_utils from synth-vhdl_stmts.
Tristan Gingold
2022-10-18
3
-142
/
+241
*
synth: handle record conversion
Tristan Gingold
2022-10-14
1
-0
/
+3
*
synth-vhdl_expr: support alias in indexed names
Tristan Gingold
2022-10-14
1
-1
/
+2
*
synth: avoid extra conversion during alias elaboration
Tristan Gingold
2022-10-14
1
-6
/
+4
*
synth: handle alias of access objects.
Tristan Gingold
2022-10-13
1
-1
/
+1
*
simul: handle last_event and last_active
Tristan Gingold
2022-10-13
2
-0
/
+16
*
elab-vhd_expr: handle more cases in exec_type_of_object
Tristan Gingold
2022-10-13
1
-1
/
+4
*
synth-vhdl_stmts(synth_verification_unit): always set instance_pool.
Tristan Gingold
2022-10-13
1
-1
/
+3
*
synth: fix crashes on scalar attribute with anonymous subtype.
Tristan Gingold
2022-10-10
1
-2
/
+2
*
simul: signal attributes in actuals
Tristan Gingold
2022-10-06
1
-2
/
+4
*
simul: complete concurrent procedure calls
Tristan Gingold
2022-10-06
2
-2
/
+5
*
simul: improve debugger (display of signals value)
Tristan Gingold
2022-10-06
3
-11
/
+48
*
elab-vhdl_objtypes(unshare): handle slice_type. Fix #2205
Tristan Gingold
2022-10-04
1
-2
/
+4
*
synth: avoid crash on invalid hdl in psl. Fix #2204
Tristan Gingold
2022-10-03
3
-17
/
+46
*
synth: improve error recovery
Tristan Gingold
2022-10-02
1
-0
/
+3
*
synth: detect division by 0, handle universal real/integer division
Tristan Gingold
2022-10-02
1
-3
/
+23
*
synth-vhdl_stmts: handle passive process. Fix ghdl/ghdl-yosys-plugin#174
Tristan Gingold
2022-10-02
1
-18
/
+204
*
synth: avoid a crash on literal overflow
Tristan Gingold
2022-10-01
1
-1
/
+10
*
synth: avoid on crash on overflow in ranges
Tristan Gingold
2022-10-01
1
-0
/
+8
*
synth: improve handling of individual generic associations
Tristan Gingold
2022-10-01
1
-17
/
+22
*
simul: finalize declarations of procedure calls
Tristan Gingold
2022-10-01
1
-0
/
+2
*
synth: handle read for floats
Tristan Gingold
2022-09-30
1
-0
/
+12
*
synth: handle float-float conversions
Tristan Gingold
2022-09-30
1
-3
/
+14
*
synth: factorize code
Tristan Gingold
2022-09-30
1
-8
/
+1
*
simul: handle quiet attribute
Tristan Gingold
2022-09-29
2
-5
/
+16
*
synth: handle guard signal in debugger
Tristan Gingold
2022-09-28
1
-0
/
+1
*
simul: handle last_value attribute
Tristan Gingold
2022-09-28
2
-0
/
+8
*
synth: handle guard signal in expressions
Tristan Gingold
2022-09-28
2
-0
/
+2
*
synth: handle null-range loops
Tristan Gingold
2022-09-28
4
-17
/
+37
*
synth: handle names in record aggregate targets
Tristan Gingold
2022-09-28
1
-0
/
+12
*
synth: handle array target aggregate
Tristan Gingold
2022-09-27
1
-2
/
+6
*
synth: handle error on variable default value
Tristan Gingold
2022-09-27
1
-0
/
+5
*
synth-vhdl_eval: handle nor, nand
Tristan Gingold
2022-09-26
1
-0
/
+21
*
synth: handle attributes in configurations
Tristan Gingold
2022-09-26
2
-1
/
+12
*
synth: improve error checks (type conversion, string literals)
Tristan Gingold
2022-09-25
3
-33
/
+37
*
synth: rework error procedure, always pass the instance
Tristan Gingold
2022-09-25
14
-251
/
+401
*
synth-vhdl_eval: handle vhdl-87 array array concatenation
Tristan Gingold
2022-09-25
1
-2
/
+31
*
synth-vhdl_stmts: fix missing newline in default assertion messages
Tristan Gingold
2022-09-25
1
-3
/
+3
*
synth: handle default expression for IN variables in assocs
Tristan Gingold
2022-09-25
1
-4
/
+10
*
synth: handle selected names in targets
Tristan Gingold
2022-09-25
1
-1
/
+2
*
synth-vhdl_eval: handle null-null in array concatenations
Tristan Gingold
2022-09-25
1
-0
/
+6
*
simul: gather disconnection specifications, create guard signal
Tristan Gingold
2022-09-25
1
-3
/
+3
*
synth: ignore groups and group templates
Tristan Gingold
2022-09-25
2
-0
/
+12
*
synth: handle attribute names
Tristan Gingold
2022-09-25
1
-13
/
+16
*
synth: handle individual subprogram associations for expressions
Tristan Gingold
2022-09-25
1
-55
/
+61
*
synth: rework association conversions
Tristan Gingold
2022-09-25
2
-28
/
+64
*
synth-vhdl_stmts: rework for subprogram associations (WIP)
Tristan Gingold
2022-09-25
1
-57
/
+36
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