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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-28 06:54:29 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-28 06:54:29 +0200 |
| commit | 8c367d78bc621b9f339042f5d456da94dd0b7861 (patch) | |
| tree | 2ce0c70ee8e896f268f4915dbc1dac6f2fc0ba79 /src/synth | |
| parent | 2efee206687fae7c8812cf7e094808a6cd733d5b (diff) | |
| download | ghdl-8c367d78bc621b9f339042f5d456da94dd0b7861.tar.gz ghdl-8c367d78bc621b9f339042f5d456da94dd0b7861.tar.bz2 ghdl-8c367d78bc621b9f339042f5d456da94dd0b7861.zip | |
synth: handle guard signal in expressions
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synth-vhdl_expr.adb | 1 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb index 204a28f04..fdbd5c302 100644 --- a/src/synth/synth-vhdl_expr.adb +++ b/src/synth/synth-vhdl_expr.adb @@ -672,6 +672,7 @@ package body Synth.Vhdl_Expr is | Iir_Kind_Variable_Declaration | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Signal_Declaration + | Iir_Kind_Guard_Signal_Declaration | Iir_Kind_Interface_Constant_Declaration | Iir_Kind_Constant_Declaration | Iir_Kind_Iterator_Declaration diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index bf30d8e08..d53773ded 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -139,6 +139,7 @@ package body Synth.Vhdl_Stmts is Assign_Base (Inter_Inst); when Iir_Kind_Variable_Declaration | Iir_Kind_Signal_Declaration + | Iir_Kind_Guard_Signal_Declaration | Iir_Kind_Constant_Declaration | Iir_Kind_File_Declaration | Iir_Kind_Non_Object_Alias_Declaration |