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| author | Tristan Gingold <tgingold@free.fr> | 2022-10-01 18:19:51 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-10-01 18:19:51 +0200 |
| commit | 8ac45f50fa908c6498801933b67d949f3f0923ca (patch) | |
| tree | f0662dd1971dc292ccb1cb0ddba106402626f48c /src/synth | |
| parent | 842dc4a42232c559d0ff6c52b40fc40559c7fa30 (diff) | |
| download | ghdl-8ac45f50fa908c6498801933b67d949f3f0923ca.tar.gz ghdl-8ac45f50fa908c6498801933b67d949f3f0923ca.tar.bz2 ghdl-8ac45f50fa908c6498801933b67d949f3f0923ca.zip | |
synth: improve handling of individual generic associations
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/elab-vhdl_insts.adb | 39 |
1 files changed, 22 insertions, 17 deletions
diff --git a/src/synth/elab-vhdl_insts.adb b/src/synth/elab-vhdl_insts.adb index 772c45fc1..24c4d5b93 100644 --- a/src/synth/elab-vhdl_insts.adb +++ b/src/synth/elab-vhdl_insts.adb @@ -63,12 +63,16 @@ package body Elab.Vhdl_Insts is Inter_Chain : Node; Assoc_Chain : Node) is + use Elab.Memtype; Marker : Mark_Type; Inter : Node; Inter_Type : Type_Acc; Assoc : Node; Assoc_Inter : Node; Actual : Node; + Formal_Typ : Type_Acc; + Formal_Base : Valtyp; + Formal_Offs : Value_Offsets; Val : Valtyp; begin Mark_Expr_Pool (Marker); @@ -80,6 +84,7 @@ package body Elab.Vhdl_Insts is case Iir_Kinds_Interface_Declaration (Get_Kind (Inter)) is when Iir_Kind_Interface_Constant_Declaration => Inter_Type := Elab_Declaration_Type (Sub_Inst, Inter); + Formal_Base := No_Valtyp; case Get_Kind (Assoc) is when Iir_Kind_Association_Element_Open => @@ -88,9 +93,22 @@ package body Elab.Vhdl_Insts is (Sub_Inst, Actual, Inter_Type); when Iir_Kind_Association_Element_By_Expression => Actual := Get_Actual (Assoc); - -- FIXME: Inter_Type is not correct for individual assoc + if Get_Whole_Association_Flag (Assoc) then + Formal_Typ := Inter_Type; + else + declare + use Synth.Vhdl_Stmts; + Formal : constant Node := Get_Formal (Assoc); + Dyn : Dyn_Name; + begin + Synth_Assignment_Prefix + (Syn_Inst, Sub_Inst, Formal, + Formal_Base, Formal_Typ, Formal_Offs, Dyn); + pragma Assert (Dyn = No_Dyn_Name); + end; + end if; Val := Synth_Expression_With_Type - (Syn_Inst, Actual, Inter_Type); + (Syn_Inst, Actual, Formal_Typ); when Iir_Kind_Association_Element_By_Individual => Val.Typ := Synth_Subtype_Indication (Syn_Inst, Get_Actual_Type (Assoc)); @@ -121,21 +139,8 @@ package body Elab.Vhdl_Insts is Create_Object (Sub_Inst, Inter, Val); else -- Modify the generic. - declare - use Synth.Vhdl_Stmts; - use Elab.Memtype; - Base : Valtyp; - Typ : Type_Acc; - Offs : Value_Offsets; - Dyn : Dyn_Name; - begin - Synth_Assignment_Prefix - (Syn_Inst, Sub_Inst, Get_Formal (Assoc), - Base, Typ, Offs, Dyn); - pragma Assert (Dyn = No_Dyn_Name); - Copy_Memory (Base.Val.Mem + Offs.Mem_Off, - Get_Memory (Val), Typ.Sz); - end; + Copy_Memory (Formal_Base.Val.Mem + Formal_Offs.Mem_Off, + Get_Memory (Val), Formal_Typ.Sz); end if; Release_Expr_Pool (Marker); |