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path: root/src/synth/synth-vhdl_stmts.adb
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* synth-environment: add Loc parameter to Add_Conc_AssignTristan Gingold2022-07-111-1/+1
* synth-vhdl_stmts: fix handling of instantiated subprogramsTristan Gingold2022-06-061-1/+3
* synth-vhdl_stmts: handle alias in assignment expressionTristan Gingold2022-06-061-2/+1
* synth-vhdl_stmts: do not convert out variable on callTristan Gingold2022-05-311-3/+8
* synth-vhdl_stmts: export Synth_Subprogram_Back_AssociationTristan Gingold2022-05-311-7/+10
* synth-vhdl_stmts: export two procedures, adjust assertion messageTristan Gingold2022-05-291-5/+6
* synth: move procedure call copyback values in contextTristan Gingold2022-05-251-69/+25
* vhdl: move Is_Copyback_Parameter to vhdl-utilsTristan Gingold2022-05-251-12/+2
* synth: add value_dyn_alias in elab-vhdl_valuesTristan Gingold2022-05-251-66/+125
* elab-vhdl_objtypes: use value_offsets for record elements offset.Tristan Gingold2022-05-241-4/+1
* synth-vhdl_stmts: minor refactoringTristan Gingold2022-05-241-12/+23
* synth-vhdl_stmts: rework synth_subprogram_associationTristan Gingold2022-05-231-35/+35
* synth: use same elements for unbounded arrays and vectorsTristan Gingold2022-05-221-4/+4
* synth: merge value for type_vector and type_arrayTristan Gingold2022-05-221-2/+2
* synth: use unidimentional arrays in type_acc. Factorize code.Tristan Gingold2022-05-221-2/+4
* synth-vhdl_stmts: write generic procedure Assign_Aggregate.Tristan Gingold2022-05-211-14/+16
* synth-vhdl_stmts: avoid a crash after an error. Fix #2063Tristan Gingold2022-05-181-1/+4
* synth-vhdl_stmts: add comments about report statementsTristan Gingold2022-05-181-5/+51
* synth-vhdl_stmts: add a commentTristan Gingold2022-05-171-0/+2
* fix: avoid "pragma Unreferenced given" warnings with GCC 12Xiretza2022-05-141-1/+1
* synth-vhdl_stmts: export synth_targetTristan Gingold2022-05-121-35/+0
* synth: add a flag to force creation of variablesTristan Gingold2022-05-111-2/+1
* synth: add current_stmt, minor reworkTristan Gingold2022-05-091-61/+64
* synth-vhdl_stmts: handle static evaluation for cond variable assignmentTristan Gingold2022-04-281-18/+53
* synth-vhdl_stmts: add implicit conversion for cond assignmentTristan Gingold2022-04-271-0/+5
* synth-vhdl_stmts: check subtype compatibility for scalar signal assoc.Tristan Gingold2022-04-151-1/+58
* synth: do not emit a warning for the gclk attribute. Fix #2035Tristan Gingold2022-04-131-1/+2
* synth: handle type declarations in vunit. Fix #2034Tristan Gingold2022-04-131-11/+15
* synth: add support for subtype declaration in vunits. Fix #2033Tristan Gingold2022-04-131-2/+4
* synth-vhdl_stmts: emit an error message on missing return. Fix #2019Tristan Gingold2022-04-061-1/+3
* synth: add debug_btTristan Gingold2022-03-081-0/+1
* synth: handle concatenation of unbounded types. Fix #1993Tristan Gingold2022-03-081-2/+2
* synth: properly propagate bound errors. Fix #1972Tristan Gingold2022-02-171-2/+5
* synth: adjust handling of subprogram calls in package instantiation. Fix #1947Tristan Gingold2022-01-161-3/+14
* vhdl/psl: handle PSL inherit spec. For #1899Tristan Gingold2021-11-051-15/+17
* synth: Support alias declarations in vunittmeissner2021-11-021-2/+7
* synth: do full elaboration before synthesisTristan Gingold2021-11-011-146/+85
* synth: reject wait statement. Fix #1903Tristan Gingold2021-10-291-0/+3
* synth: Support PSL declarations in inline PSLtmeissner2021-10-141-1/+2
* synth: add support for sequence instance in vunit. Fix #1889Tristan Gingold2021-10-131-2/+4
* vhdl-canon: recurse for default block configuration of a vunit.Tristan Gingold2021-09-121-7/+2
* synth-vhdl_stmts: fix crash on nested if-generate statement in vunits.Tristan Gingold2021-09-111-2/+5
* vhdl: allow constants in vunit declarations. Fix #1856Tristan Gingold2021-09-081-0/+2
* synth-vhdl_stmts.adb: do not expect configuration for vunit.Tristan Gingold2021-09-011-3/+3
* synth: handle PSL async_abort and sync_abort. For #1654Tristan Gingold2021-08-311-1/+33
* synth-vhdl_stmts: fix a crash on never triggered PSL assertion.Tristan Gingold2021-08-291-0/+6
* synth: improve result of is_positiveTristan Gingold2021-08-291-1/+4
* synth: do not remove signals with a keep attribute.Tristan Gingold2021-08-271-1/+2
* vhdl: remove iir_kind_anonymous_signal_declaration (now unused)Tristan Gingold2021-08-241-2/+0
* synth-vhdl_stmts: add location on AddidxTristan Gingold2021-06-211-0/+2
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