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| author | Tristan Gingold <tgingold@free.fr> | 2022-05-22 09:09:14 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-05-22 09:09:14 +0200 |
| commit | 946320e0984df406f0e3c50cd3db0fb49df5ec9b (patch) | |
| tree | 97d51eff8e649cacf5ad081f7dd9258553ddb2b2 /src/synth/synth-vhdl_stmts.adb | |
| parent | c56080fed0b46083cf138962c5bb125ea08bfa0e (diff) | |
| download | ghdl-946320e0984df406f0e3c50cd3db0fb49df5ec9b.tar.gz ghdl-946320e0984df406f0e3c50cd3db0fb49df5ec9b.tar.bz2 ghdl-946320e0984df406f0e3c50cd3db0fb49df5ec9b.zip | |
synth: merge value for type_vector and type_array
Diffstat (limited to 'src/synth/synth-vhdl_stmts.adb')
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 14302134d..02405dd25 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -858,8 +858,8 @@ package body Synth.Vhdl_Stmts is when Type_Discrete => return False; when Type_Vector => - if V.Typ.Vec_El = Logic_Type then - for I in 1 .. Size_Type (V.Typ.Vbound.Len) loop + if V.Typ.Arr_El = Logic_Type then + for I in 1 .. Size_Type (V.Typ.Abound.Len) loop if Ignore_Choice_Logic (Read_U8 (V.Val.Mem + (I - 1)), Loc) then return True; |