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| author | Tristan Gingold <tgingold@free.fr> | 2021-08-28 12:19:39 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-08-29 11:50:17 +0200 |
| commit | 886fdeb52c4d37540e854dc2d57f8f95de09d4dc (patch) | |
| tree | 2bed706cf4eedcba44bd7a3a35e6b3b9d723f82e /src/synth/synth-vhdl_stmts.adb | |
| parent | 132fde15a4d4bffd31bff341dfeaf11317c82130 (diff) | |
| download | ghdl-886fdeb52c4d37540e854dc2d57f8f95de09d4dc.tar.gz ghdl-886fdeb52c4d37540e854dc2d57f8f95de09d4dc.tar.bz2 ghdl-886fdeb52c4d37540e854dc2d57f8f95de09d4dc.zip | |
synth: improve result of is_positive
Diffstat (limited to 'src/synth/synth-vhdl_stmts.adb')
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index bfa3db4be..89c96012a 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -1071,7 +1071,9 @@ package body Synth.Vhdl_Stmts is when Unknown => if Prev_Val = Null_Memtyp then -- First use of previous value. - if not Is_Static_Wire (Wid) then + if Get_Kind (Wid) /= Wire_Variable + or else not Is_Static_Wire (Wid) + then -- The previous value is not static. return Null_Memtyp; end if; @@ -2262,6 +2264,7 @@ package body Synth.Vhdl_Stmts is is M : Memtyp; begin + pragma Assert (Get_Kind (Wid) = Wire_Variable); if not Is_Static_Wire (Wid) then return False; end if; |