iCE40/ghdl - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	synth: rework range.	Tristan Gingold	2019-07-26	1	-1/+44
*	synth: handle array aggregate.	Tristan Gingold	2019-07-26	1	-26/+31
*	synth: array inequality, integer in choices.	Tristan Gingold	2019-07-25	1	-0/+7
*	vhdl+synth: recognize /= to std_logic_unsigned.	Tristan Gingold	2019-07-25	1	-0/+3
*	synth: save and display locations for instances.	Tristan Gingold	2019-07-25	1	-64/+116
*	synth: do not consider (unrecognized) ieee functions as user functions.	Tristan Gingold	2019-07-24	1	-0/+19
*	synth: handle resize.	Tristan Gingold	2019-07-24	1	-0/+15
*	synth: add more operators.	Tristan Gingold	2019-07-23	1	-1/+34
*	synth: fix to_unsigned.	Tristan Gingold	2019-07-23	1	-2/+2
*	synth: add and merge phi within a function.	Tristan Gingold	2019-07-20	1	-0/+5
*	synth: fix aggregate vectorize direction.	Tristan Gingold	2019-07-20	1	-5/+5
*	synth: add > and >= operators (#870)	Pepijn de Vos	2019-07-16	1	-2/+15
*	synth: handle choices by range in aggregates.	Tristan Gingold	2019-07-15	1	-5/+16
*	synth: handle anonymous signals.	Tristan Gingold	2019-07-14	1	-0/+3
*	synth: handle simple user function calls.	Tristan Gingold	2019-07-06	1	-15/+60
*	synth: support top-level generics.	Tristan Gingold	2019-07-06	1	-0/+8
*	synth: handle some "/=".	Tristan Gingold	2019-07-04	1	-0/+3
*	synth: handle PSL restrict directive (WIP).	Tristan Gingold	2019-07-04	1	-1/+2
*	synth: add concat_array function.	Tristan Gingold	2019-07-04	1	-36/+44
*	synth: emit an error for non-constant bounds.	Tristan Gingold	2019-07-04	1	-0/+4
*	synth-expr: remove useless code.	Tristan Gingold	2019-07-02	1	-5/+1
*	synth: destroy iterator after for-loop.	Tristan Gingold	2019-07-01	1	-0/+2
*	synth: improve handling of dynamic slices, add a	Tristan Gingold	2019-07-01	1	-3/+30
*	synth: add dyn_insert module.	Tristan Gingold	2019-07-01	1	-9/+9
*	synth: add types_utils package.	Tristan Gingold	2019-07-01	1	-3/+1
*	synth: handle for-loop statements.	Tristan Gingold	2019-07-01	1	-1/+2
*	synth: handle more concat.	Tristan Gingold	2019-06-30	1	-0/+19
*	synth: handle more comparisons.	Tristan Gingold	2019-06-30	1	-11/+29
*	synth: handle std_logic_unsigned."+"	Tristan Gingold	2019-06-30	1	-1/+2
*	synth: handle "=" from std_logic_unsigned.	Tristan Gingold	2019-06-29	1	-1/+2
*	vhdl: move annotations from simul to vhdl.	Tristan Gingold	2019-06-29	1	-1/+1
*	synth: disp_vhdl: merge literals.	Tristan Gingold	2019-06-28	1	-0/+7
*	synth: Move get_input_net to netlists.utils.	Tristan Gingold	2019-06-28	1	-0/+1
*	synth: handle some functions from math_real.	Tristan Gingold	2019-06-28	1	-1/+43
*	synth: add get_input_net helper.	Tristan Gingold	2019-06-28	1	-7/+7
*	synth: add syn_extract for dynamic slices.	Tristan Gingold	2019-06-28	1	-54/+205
*	synth: handle slice assignment.	Tristan Gingold	2019-06-25	1	-31/+32
*	synth: add insert gate.	Tristan Gingold	2019-06-24	1	-16/+23
*	synth: handle more operators.	Tristan Gingold	2019-06-23	1	-4/+15
*	synth: remove unused Value_Logic.	Tristan Gingold	2019-06-23	1	-13/+5
*	synth: handle ult comparison.	Tristan Gingold	2019-06-23	1	-28/+36
*	synth: handle more predefined functions.	Tristan Gingold	2019-06-23	1	-3/+74
*	synth-expr: clarify error message.	Tristan Gingold	2019-06-20	1	-2/+7
*	synth: get rid of execution and elaboration.	Tristan Gingold	2019-06-19	1	-254/+450
*	synth-expr: use Node instead of Iir (renaming).	Tristan Gingold	2019-06-13	1	-32/+32
*	synth-expr: handle choice_by_expression in aggregates.	Tristan Gingold	2019-06-12	1	-3/+30
*	synth: handle enumerated types.	Tristan Gingold	2019-06-12	1	-9/+12
*	synth-expr: resize for uns-uns operations.	Tristan Gingold	2019-06-12	1	-18/+28
*	synth: support conditional signal assignments.	Tristan Gingold	2019-06-08	1	-0/+6
*	synth: handle integer +/- for constants.	Tristan Gingold	2019-06-08	1	-21/+37